Abstract: A performance boosting method of a semiconductor device includes monitoring input of a user and an amount of system usage, generating user system information in response to an event occurring, the user system information including first information and the amount of system usage, the first information regarding input of the user, adaptively determining a performance boosting target value based on the user system information, and boosting an operating frequency according to the performance boosting target value.

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract: A receiver includes a first receiving circuit that receives a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals. The first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals.

Abstract: Data storage device has a super-capacitor, a control unit with multiple operational states, non-volatile memory, and a bus connected to a computing device with a separate power source. The control unit state is set by the power level of the computing device and the super-capacitor. In a backup state, the control unit stores backup data from the computing device in the non-volatile memory using power from the super-capacitor. In an inactive state, the control unit does not receive power from the super-capacitor. The control unit is set to the backup state when the device power level is less than a first threshold and the super-capacitor voltage level is greater than a second threshold. The control unit is set to the inactive state when the super-capacitor voltage level decreases below a third threshold that is less than the second threshold by more than the dielectric absorption voltage gain of the super-capacitor.

Abstract: Embodiments of the present disclosure include a power management unit for controlling power in a microcontroller. The unit causes a first voltage to be provided in an active mode. In a sleep mode, the unit determines whether a supply voltage is less than an upper reference voltage and, if so, cause a second voltage greater than the first voltage to be provided. If not, the unit inhibits operation of voltage regulation of power supplied to the microcontroller. After inhibition of operation of voltage regulation, the unit determines whether the supply voltage has fallen to a lower reference voltage and, if so, applies the second voltage to the microcontroller.

Abstract: According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.

Abstract: A financial device may include: one or more modules each including a storage unit; and a main control unit configured to disconnect power to the one or more modules after operation information is stored in the storage unit, when entering a power saving mode. The storage unit may store the operation information of the corresponding module of the one or more modules, when entering the power saving mode.

Abstract: A microminiature personal computer that is connected to external devices using standard interfaces for information input and output. The microminiature personal computer has an interconnected processor, a memory, a security module, a network module, and connectors. At least part of memory should be non-volatile to keep operating system, drivers to work with external devices, programs and data. The microminiature personal computer does all its processing and all its programs are running inside its memory while external computing device is used only for information input and output through a connector and a windowing system thus ensuring security of both systems and lack of unauthorized interaction between them.

Abstract: A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.

Abstract: A clock generator outputs a processor clock that serves as an operation reference for a processor for use in a content protection system. The clock generator includes a direct digital synthesis and a random number generator. The direct digital synthesizer includes a phase accumulator and outputs the processor clock. The phase accumulator accumulates a setup value in synchronization with a reference clock. The random number generator generates random numbers. The setup value changes based on the random numbers.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

Abstract: A register clock driver for a DDR5 memory is presented. A register clock driver (RCD) can include a logic having one or more input channels, each of the one or more input channels receiving input signals; and a plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on each of the one or more input channels to the associated plurality of ranked output ports according to control signals. The RCD can operate in a default mode, wherein input signals from the input channels are output to both of the output ports associated with that channel, or can operate in a non-default mode where input signals from the input channels are sent to the appropriate ranked output port associated with that channel. In either case, unused signaling on the output ports is held high.

Abstract: Provided is an information processing apparatus including a processor configured to control a system of the information processing apparatus, a power source controller configured to perform control of power supply to the system and to turn off a power source of the power source controller in standby mode in which a power source of the processor is turned off, a memory configured to store information in standby mode, and a power supply unit configured to perform power supply to the memory in standby mode.

Abstract: Disclosed are various embodiments of adaptive management of a device. The adaptive management includes, e.g., power management, energy management, and diagnostics. In one embodiment, a device including a power management unit (PMU) communicatively coupled to a processor is configured to transmit a status notification to the processor in response to an interrupt signal; obtain a high level state command from the processor in response to the status notification, and modify power operation of the device in response to the high level state command. In another embodiment, a method for charging a power source includes obtaining, by a PMU of a device, operational characteristics of a power supply in communication with the device; determining a power supply type based at least in part upon the operational characteristics; and controlling charging of the power source based at least in part upon the power supply type.

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

Abstract: A processor capable of executing predetermined processing includes: a communication interface for communicating with a host device which requests the execution of the processing; a main control unit configured to control the execution of the processing; a notification unit which does not proceed to a power saving mode but executes notification processing for allowing the host device to detect that an operating mode of the main control unit is in the power saving mode when the main control unit proceeds to the power saving mode reducing power consumption; and a state switching unit configured to allow the communication interface to proceed to a power saving state of which power consumption is smaller than that of a normal state when the communication interface receives a power saving command from the host device.

Abstract: A method may include monitoring a power capacity of power supply units of a chassis, responsive to determining that the power capacity is lesser than a first minimum power capacity required for full operation of all of the modular information handling systems and information handling resources of the chassis and greater than a threshold power capacity for triggering operation in a minimal operational state of the chassis, causing at least one of the plurality of modular information handling systems and the information handling resources to reduce power consumption, and responsive to determining that the power capacity is lesser than the threshold power capacity and greater than a second minimum power capacity for a minimal operational state of the modular information handling systems and information handling resources, causing at least one of the plurality of modular information handling systems and the information handling resources to operate in the minimal operational state.

Abstract: A computer mainboard includes components intended for operating a computer, a control logic that controls voltage supply of the computer mainboard, and a connector plug that receives at least one supply voltage (+12V DC) specified for the computer mainboard, an auxiliary voltage (Vin_ext_DC) and a monitoring signal (Vin_ext_OK) that indicates the presence of an external supply voltage (VEXT_DC, VEXT_AC) that has a predetermined specification, wherein the control logic is configured to detect the monitoring signal (Vin_ext_OK) via the connector plug and, after detection of the monitoring signal (Vin_ext_OK), to generate a first control signal (EN_REG_EB#) and output it to the outside via the connector plug so that, depending thereon, an external voltage supply device can be activated to provide the at least one supply voltage (+12V DC) specified for the computer mainboard from the external supply voltage (VEXT_DC, VEXT_AC).

Abstract: A method for managing a battery-powered device. In one embodiment, the method includes a computer processor identifying a first plan of activities to be performed by a battery-powered device, where the first plan of activities includes an estimated first power consumption for the first plan of activities. The method further includes determining a level of power of a first battery of the battery-powered device. The method further includes generating a first set of implementation details that manage power consumption within the battery-powered device while performing the first plan of activities, based on the estimated first power consumption and the determined power level of the first battery of the battery-powered device. The method further includes applying the first set of implementation details to the battery-powered device to perform the first plan of activities.