Abstract: The present invention discloses a method for trusted booting of PLC based on a measurement mechanism, comprising the following steps: a step of initializing self firmware verification; a step of reading and computing firmware information about a PLC; a step of checking and storing one by one; and a step of verifying at the operation start stage. In the method of the present invention, a chip with a trusted function is used as a core of hardware computation. The PLC extends a Flash bus for loading by hardware of the method of the present invention. The hardware of the method of the present invention recognizes necessary boot information, verifies the integrity of the boot loader necessary for the PLC system through the integrity check method and ensures that the booted PLC system is in a trusted state. On the basis of ensuring validity and feasibility for the safety of a terminal device, the present invention can build a safe and trusted industrial control system operating environment.

Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: Within a communication system that includes multiple communication channels, a low-power mode of operation and a higher-power mode of operation are provided. Each channel is allocated to one of several groups, based on criteria such as whether power is allocated to that channel in low power mode, and whether power was allocated to that channel in a previous high power mode. Initial power levels for each channel for each mode are approximated using an interpolation rule known to both the receive and the transmitter. The system switches between modes according to a PMD pre-defined schedule. When a new power mode begins, the receiver measures signal power received on each channel and then transmits corrective information sufficient to allow adaptation of power levels to achieve PMD pre-defined levels of received power.

Abstract: An apparatus and a method for controlling power consumption associated with a computing device having first and second processors configured to perform different types of operations includes providing a user interface that allows, during normal operation of the computing device, at least one of: (i) a user selection of desired performance levels of the first and second processors relative to one another, such that higher desired performance levels of one processor correspond to lower desired performance levels of the other processor, and (ii) a user selection of a desired performance level of the first processor and a user selection of a desired performance level of the second processor, the two user selections being made independently of one another. The apparatus and method control, during normal operation of the computing device, performance levels of the processors in response to the one or more user selections of the desired performance levels.

Abstract: Embodiments described herein improve availability of a power plane in a network device by using a PoE manager that is separate from an operating system in the network device. For example, when the operating system (or a PoE application executing in the operating system) becomes unavailable, either because of failure or system upgrade, the PoE manager continues managing a power plane in the network device such that connected PDs continue to receive DC power. Stated differently, by using a PoE manager that is separate from the operating system, there is no fate sharing between the PoE manager and the operating system. If the operating system is unavailable, the PoE manager continues to provide the same power allotment to the PDs. As such, updates and failures which previously made the power plane unavailable no longer affect the power supplied to the PDs.

Abstract: An electronic device includes a processor, a timer and a memory device. The memory device stores a value for power-on hours. During the process of booting the electronic device, the processor triggers the timer to start counting down. When the timer expires, the processor updates the value of power-on hours.

Abstract: A method for power control includes determining a load power of a load coupled to an output of an isolated AC/DC power supply. The method also includes, when the determined load power is less than a first threshold load power, providing the load power to the load from an interim power source.

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

Abstract: Systems, apparatuses, methods, and computer readable mediums for performing a lazy bare metal restore process. A system may boot into a mini-OS environment and recover only the OS volumes while running in the mini-OS environment. Then, the system may boot into the target OS in restricted mode, using the recovered OS volumes, wherein restricted mode is utilized so as to prevent any applications from running. While the system is running the target OS in restricted mode, the system may restore the remainder of the backup data. Then, once all of the data has been recovered, the system may boot into the target OS in normal mode.

Abstract: A method of controlling a hard disk and an electronic device, comprising: determining a number of power cycles that have been completed by the hard disk at a time point within a predetermined period of time, a power cycle including a total duration of the hard disk in a spin-on mode and an immediately neighboring spin-off mode; and in response to the number of power cycles that have been completed being below an upper limit number for the power cycles of the hard disk in the predetermined period of time, determining remaining time of the predetermined period of time starting from the time point, and determining, based on the remaining time, the number of power cycles that have been completed, and the upper limit number, a threshold idle duration for controlling the hard disk to enter the spin-off mode.

Abstract: Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.

Abstract: A Basic Input/Output System (BIOS)/Unified Extensible Firmware Interface (UEFI) on a Self-Service Terminal (SST) loads ATM resources into volatile memory of the SST during a boot of the SST in a predefined order. Each time, during an SST boot, where the order is attempting to be changed; a credential is required to change the predefined order and the credential has to be authenticated before the predefined order is changed during the SST boot.

Abstract: A processing system includes multiple processors in which first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). A third processor may be included that also operates at the first clock frequency and the first supply voltage at all times. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. A controller enables control and fast-switching between the two modes for the switchable processor.

Abstract: A semiconductor device and a semiconductor system are provided. A semiconductor device includes a monitoring circuit receiving a first operating voltage and a second operating voltage, which is different from the first operating voltage, from a Power Management Integrated Circuit (PMIC) and monitoring a duration of use of a System-on-Chip (SoC) at each of the first and second operating voltages; a processing circuit calculating a normalized value based on predetermined weight information from the duration of use of the SoC at each of the first and second operating voltages; and a voltage circuit determining whether to increase an operating voltage of the SoC by comparing the normalized value with a predetermined value.

Abstract: An information processing device includes a state determination unit. The state determination unit switches between first execution processing that executes a function of the information processing device by way of an operating system, and second execution processing that stops operation of the operating system during operation, and executes a specific function of the information processing device by way of a specific program without turning ON a power source of the information processing device. The second execution processing is not performed during execution of the first execution processing.

Abstract: In a general aspect, a computer-implemented method can include receiving, by a device including a plurality of functional elements, an indication of a service to be implemented by the device. The method can also include determining one or more functional elements of the device that are needed to implement the service. The one or more functional elements needed to implement the service can be a subset of the plurality of functional elements of the device. The method can further include initializing the device by activating the one or more functional elements needed to implement the service.

Abstract: A system may include a motion sensor configured to generate a motion signal in response to a movement of an electronic device, and at least one feature detection circuit configured to determine at least one metric based on the motion signal. The system may further include a classifying circuit configured to determine whether the electronic device is in contact with a human body based on the at least one metric.

Abstract: Systems and methods for executing multiple operating systems on a computing system without rebooting the computing system are disclosed. Embodiments may include installing a first OS and a second OS on a computing system. Embodiments may further include executing the first OS on hardware resources of the computing system. Some embodiments may also include suspending execution of the first OS, and executing the second OS on the hardware resources while execution of the first OS is suspended.

Abstract: Embodiments of a method, a device and a computer-readable storage medium are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) device involves detecting a transition of a CAN transceiver of the CAN device from a dominant state to a recessive state and in response to detecting a transition of the CAN transceiver from the dominant state to the recessive state, controlling an output impedance of the CAN transceiver to be within a predefined range of an impedance value at the dominant state while a differential driver voltage on a CAN bus connected to the CAN transceiver decreases to a predefined voltage.