Abstract: A system may include a motion sensor configured to generate a motion signal in response to a movement of an electronic device, and at least one feature detection circuit configured to determine at least one metric based on the motion signal. The system may further include a classifying circuit configured to determine whether the electronic device is in contact with a human body based on the at least one metric.

Abstract: Systems and methods for executing multiple operating systems on a computing system without rebooting the computing system are disclosed. Embodiments may include installing a first OS and a second OS on a computing system. Embodiments may further include executing the first OS on hardware resources of the computing system. Some embodiments may also include suspending execution of the first OS, and executing the second OS on the hardware resources while execution of the first OS is suspended.

Abstract: Embodiments of a method, a device and a computer-readable storage medium are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) device involves detecting a transition of a CAN transceiver of the CAN device from a dominant state to a recessive state and in response to detecting a transition of the CAN transceiver from the dominant state to the recessive state, controlling an output impedance of the CAN transceiver to be within a predefined range of an impedance value at the dominant state while a differential driver voltage on a CAN bus connected to the CAN transceiver decreases to a predefined voltage.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.

Abstract: Systems and methods are disclosed for data storage performance scaling based on external energy. In certain embodiments, a system may comprise a data storage device having an interface to communicate with an external device, a nonvolatile memory, and a circuit. The circuit may be configured to receive an indication via the interface of power resources available to the data storage device from the external device in case of a power loss event, adjust a performance metric of the data storage device to apply when accessing the nonvolatile memory during normal power availability based on the indication, and perform operations during normal power availability based on the performance metric.

Abstract: With a method of connecting SRAMs by daisy chain connection, the power state of all the SRAMs is determined uniquely. Because of this, even in the case of an SRAM of a function module in which SRAM access does not occur, the SRAM returns to the normal mode. The control apparatus includes a plurality of function modules including a memory capable of making a transition between a first power state and a second power state that is more power-saving than the first power state in accordance with a control signal. Then, control is performed so as to output a first signal that gives instructions to make a transition of the power state based on the control signal to a memory of a function module of the plurality of function modules in which processing using a function that the function module has is performed.

Abstract: A data processing apparatus includes a first processor, a second processor, a first power source which performs electric power supply to the first processor, a second power source which preforms electric power supply to the second processor, a detector which detects an abnormality of the second power source, and a switcher which is capable of switching a power supply target of the first power source between the first processor and the second processor. When an abnormality of the second power source is detected, the first processor stops an operation of the first processor, and the switcher switches the power supply target of the first power source from the first processor to the second processor after the operation of the first processor is stopped.

Abstract: A Basic Input/Output System (BIOS)/Unified Extensible Firmware Interface (UEFI) on a Self-Service Terminal (SST) processes during a boot of the SST. When a new hard disk is detected as being present and an identifier for the new hard disk is missing from a whitelist, a signed hard disk identifier is verified from storage on the new hard disk. If the signed hard disk identifier is verified: the new hard disk is authenticated, the whitelist is updated to include the new hard disk identifier, a unique identifier for BIOS/UEFI and the new hard disk identifier are written to the storage of the new hard disk, and the boot process is permitted to continue for the SST.

Abstract: Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.

Abstract: A boot secure device that performs a secure booting operation of a semiconductor system includes an external memory interface that provides an interface with an external memory, a first internal memory that stores a boot image stored in the external memory, a second internal memory that stores a hash of a first public key, a secure accelerator that verifies the boot image using the hash of the first public key, and a secure boot sequencer that includes a plurality of states and a plurality of operation and that controls the external memory interface, the first internal memory, the second internal memory, and the secure accelerator using at least one of the plurality of operations when a state transition occurs between two of the plurality of states.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for launching a device.

Abstract: Embodiments are directed to a method of optimizing power consumption in an electrical device. The method includes receiving, by a processor, instructions to enter a wait state, and identifying, by the processor, a parameter associated with the instructions to enter a wait state. The method continues with initiating, by the processor, instructions to enter a low-power mode based on the parameter, initiating, by the processor, instructions to exit a low-power mode based on the parameter, and providing, via a user interface, a user with notice of a current state of the processor. The parameter includes runtime information, instructional information, and scheduled operations.

Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

Abstract: An integrated circuit (IC) package of an electronic device includes a first input coupled to a first voltage rail and a second input coupled to a second voltage rail. The IC package further includes a set of one or more input/output (IO) pad cells and a power sequence detector coupled to the first and second voltage rails. The power sequence detector monitors the first and second voltage rails and configures the set of one or more IO pad cells to operate at one of a non-zero first voltage level or a non-zero second voltage level depending on which of the first voltage rail and the second voltage rail ramps up to a corresponding specified voltage level first.

Abstract: A computer device may include a memory configured to store instructions and a processor configured to execute the instructions to determine a device status associated with the wireless communication device and determine that a machine learning process is to be performed based on the determined device status. The processor may be further configured to execute the instructions to select a machine learning model based on the determined device status; select one or more data inputs based on the determined device status; and perform the machine learning process using the selected machine learning model and the selected one or more data inputs.

Abstract: A method and apparatus for cooperative power management by virtual machines is disclosed. In an example apparatus, a computing device includes a number of virtual machines (VMs), each sharing a resource with another of the VMs. A virtual machine monitor (VMM) includes a shared memory object accessible by the VMs, wherein the shared memory object comprises a current power state requested by a VM for the resource.

Abstract: An electronic device can include a first and second portions that are pivotally coupled to each other so that the electronic device can have at least a closed configuration and an open configuration. A magnetic sensor system can be carried by the electronic device to detect the closed configuration so that the electronic device can automatically turn to a mode, such as a sleep mode, when the electronic device is bought to the closed configuration. A magnetic sensor can have a detection axis that targets a horizontal component of a magnetic field. A triggering magnetic element can be laterally offset relative to the magnetic sensor. The magnetic sensor can also be a magneto-resistive sensor. The electronic device can also include a second set of magnetic sensor system to confirm when the electronic device is brought to the closed configuration.

Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on-die signal calibration. A calibration circuit on an integrated circuit device receives data from an active data path of the integrated circuit device and detects a variation in the received data from a calibration data pattern. An adjustment circuit on an integrated circuit device reduces a delay of an active data path of the integrated circuit device in response to detecting a first variation in received data. An adjustment circuit on an integrated circuit device increases a delay of an active data path of the integrated circuit device in response to detecting a second variation in received data.

Abstract: A power adapter for supplying electrical power to a mobile device. The power adapter may have a processor and an interface for data communication and power transmission with the mobile device, memory internal to a casing of the power adapter, and an AC/DC power conversion circuit electrically coupled to the processor. The AC/DC power conversion circuit is configured to receive an AC power input and convert the AC power input to a DC power output over the interface for the mobile device. The processor is configured to: recognize a load associated with the mobile device connected to the DC power output; set the DC power output based on the load; receive backup data from the mobile device over the interface; and store the backup data from the mobile device within the memory.