Abstract: Systems and methods are disclosed for efficient management of bus bandwidth among multiple drivers. An example method may comprise: receiving a request from a driver to map the driver to a device memory of a device to allow the driver to write data on the device memory via a bus; mapping the driver to a random access memory (RAM) such that the driver is to write the data to the RAM; reading contents of the RAM at a specified interval of time to determine whether the data written by the driver is accumulated in the RAM; responsive to determining that the data written by the driver is accumulated in the RAM, determining whether a bandwidth of the bus satisfies a bandwidth condition; and responsive to determining that the bandwidth satisfies the bandwidth condition, forwarding, via the bus, a portion of the data written by the driver in the RAM to the device memory.

Abstract: An oscillation reduction unit for a bus system. The oscillation reduction unit has two transistors, which are situated anti-serially between a first bus wire of a bus of the bus system and a second bus wire of the bus, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and a time control block for switching the two transistors and designed to switch on the two transistors while a signal on the first and/or second bus wire and/or a transmission signal, from which the signals on the first and/or second bus wire are generated, changes from a dominant state to a recessive state, and designed to switch off the two transistors if the signal on the first and/or second bus wire and/or the transmission signal is/are switched into the recessive state.

Abstract: Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets.

Abstract: A method for bandwidth allocation includes receiving requests for bus channel access from two or more master devices. Next, the method selects one of priority-based allocation or credit-based allocation. Upon selecting the priority-based allocation, the method grants bus channel access based on pre-assigned priorities for bus channel access. Upon selecting credit-based allocation, the method grants bus channel access based on pre-allocated credits for bus channel access, and the method decrements the credit from the master device that has been granted bus channel access.

Abstract: A bus driver for driving a differential data bus can be in a dominant data bus state and in a recessive data bus state. In the dominant data bus state, the bus driver connects the first and second single-wire data bus lines to a first and second electrical potential and temporarily does not drive the first and second single-wire data bus lines in the recessive data bus state. In the recessive data bus state after a change from the dominant data bus state to the recessive data bus state, bus driver connects the first and second single-wire data bus lines to a fourth electrical potential for an active time.

Abstract: A system for camera device discovery and enumeration detects a camera device connected to a computing device using a Universal Plug and Play (UPnP) protocol and generates a device object corresponding to the detected camera device with a user-mode camera driver. The user-mode camera driver associated with an operating system executing on the computing device. The system registers the generated device object with the operating system to provide a direct interface from the operating system to the camera device and to make the camera device available to a plurality of applications executing on the computing device and commands the camera device from at least one of the plurality of applications via the registered device object through the operating system, thereby improving the functioning of the computing device and the user experience.

Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

Abstract: A system having information equipment connected in a daisy chain, where power supply control of the daisy chain-connected information equipment is performed without having to add a dedicated power supply control device. In a daisy chain connection system, second information equipment comprise a control unit and a power supply unit, and a first information equipment and the control unit of the second information equipment include a communication circuit capable of wired communication, and the first information equipment and the power supply unit of the second information equipment include a wireless circuit capable of wireless communication. When turning OFF a power supply to any one of the second information equipment, the first information equipment requests the power supply unit to stop the power supply by using wireless communication, and the power supply unit performs control for stopping the power supply to the control unit according to the request.

Abstract: A processing subsystem/endpoint subsystem connection configuration system includes a plurality of processing subsystems and a multi-endpoint adapter device that provides a plurality of endpoint subsystems. A bus exchange switch device couples the plurality of processing subsystems to the plurality of endpoint subsystems, and a connection configuration engine is coupled to the multi-endpoint adapter device and the bus exchange switch device. The connection configuration engine receives a connection resource request that requests connection resources for a first processing subsystem that is included in the plurality of processing subsystems. Based on the connection resource request, the connection configuration engine causes at least one of the plurality of endpoint subsystems to perform a first connection resource change operation. The connection configuration engine then configures the bus exchange switch device to provide the connection resources for the first processing subsystem.

Abstract: In general, in one aspect, the invention relates to a method for managing pool device resources, the method including obtaining, by a distribution manager, a resource use request from a user application, wherein the user application and the distribution manager are operating on a pool device, identifying a peripheral component interconnect (PCI) bus device, wherein the PCI bus device is located on a second pool device and connected to a pool device resource on the second pool device, and initiating access to the PCI bus device using a virtual switch operating on the pool device.

Abstract: An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: The application discloses an electronic device with a USB Type-C connector, which is able to be coupled to another electronic device. The electronic device includes a control unit, a switch unit and a charge conversion unit. The control unit outputs a first control signal according to a result of power supply handshaking between the electronic device and the other electronic device. The state of the first control signal determines whether the other electronic device supplies power to the electronic device. The switch unit is coupled to the control unit, and receives a supply voltage output by the other electronic device, and the switch unit determines whether to output the supply voltage according to the state of the first control signal. The charge conversion unit is coupled to the switch unit. The charge conversion unit converts the supply voltage into a target voltage to supply power to the electronic device.

Abstract: A line replacement unit includes a terminal controller, and a plastic optical fiber serial interface module (POFSIM) coupled between the terminal controller and the data bus. The POFSIM is configured to transmit digital optical signals to the data bus based on electrical signals received from the terminal controller, and transmit electrical signals to the terminal controller based on digital optical signals received from the data bus.

Abstract: A device includes a first input/output (I/O) port for communication with an external processor, a second I/O port for communication with a second device, and an interface adaptor supporting communication through the first and second I/O ports via a protocol having a plurality of layers, including an application layer, a physical layer, and a physical adaptor layer. The application layer processes information according to an application layer format and the physical adaptor layer processes information according to a physical adaptor layer format. The device receives from the external processor through the first I/O port a request in the application layer format that one or more communication conditions be set for a physical layer of the second device, converts the request from the application layer format to the physical adaptor layer format, and sends the converted request in the physical adaptor layer format to the second device through the second I/O port.

Abstract: An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.

Abstract: The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. A bus IF is constituted by a master having an initiative of communication and a slave that communicates with the master under the control of the master. Additionally, the slave is provided with a detection unit that, when detecting a change in level of a signal line representing a declaration of initiation or end of communication by the master, outputs a detection signal indicating that the change in level of the signal line representing a declaration of initiation or end of communication has been detected, and a false detection avoidance unit that invalidates output of the detection signal during a specific time slot set in advance. The present technology can be applied to, for example, a bus IF that performs communication in conformity with the I3C standard.