Abstract: A fault tolerant computer system distributes audit trail files containing audit records, across an arbitrary number of disk volumes. After one audit trail file becomes full, audit records are directed toward a next audit trail file stored on a different disk volume. Storage of newly generated audit rotates through the disk volumes in round-robin fashion. Full audit trail files are eventually archived and their space becomes available again for renaming and storage of newly generated audit records. The number of audit records available for on-line recovery after a failure is not limited to the storage capacity of any single disk volume. Furthermore, there is no contention for disk access between archiving of full audit trail files and storage of newly generated audit records.

Abstract: A method for testing a sequential circuit by applying a number of test vectors to the primary inputs of the sequential circuit between each application of a clock circuit. Once the sequential circuit enters a state and that state is a necessary condition for detecting various faults, test vectors are applied to the primary inputs of the sequential circuit, which vectors are designed to propagate all fault effects that can be propagated at that state of the circuit. Once those vectors have been applied, a state-advancing vector is applied immediately before the application of the clock. The state-advancing vector is designed to condition the circuit to allow more fault effects to be propagated to the primary outputs, and to propagate fault effects into the storage elements of the circuit.

Abstract: An interface circuit for keyboards and other serial peripheral devices that adds loopback capability through multiplexers in the clock and data lines, and also provides a receiver clock delayed from the transmitter clock to avoid race conditions between the data and clock lines. The circuit also provides a means of forcing a zero bit onto the data line after a byte is sent, to indicate to the transmitter that the byte was received by the receiver. The circuit also provides a way to hold off the transmitter, to simulate the normal keyboard action of holding off transmitter while it processes the character just sent.

Abstract: A portable tester for local area networks comprising a AUI circuit coupled to a media specific transceiver, a battery, a push-to-test switch and four light emitting diodes and an RJ45 jack for each of a personal computer and a network hub. When the push-to-test switch is pushed, power is applied to the media access unit and a link pulse is generated for coupling via a PC jack to a personal computer plugged into that jack. The link pulse is also coupled to any network hub plugged into a hub jack. The PC and network hub cannot both be simultaneously connected. If whichever unit is connected receives the link pulse and generates its own link pulse which is received by the tester, a link status LED is lit green. Otherwise, it is left dark. If the unit connected outputs a data packet in response to receipt of the link pulse, a receive data LED is lit green. Otherwise, it is left dark. If the link pulse is positive-going on the correct line, a polarity LED is lit green. Otherwise, it is left dark.

Abstract: The data contents of up to two concurrently failed or erased DASDs can be reconstituted where the data is distributed across M DASDs as an (M-1)*M block array and where (1) the (M-1)st DASD contains the simple parity taken over each of the array diagonals in diagonal major order in the same mode (odd/even) as that exhibited by the major diagonal of the array and (2) where the M-th DASD contains the simple even parity over each of the rows in row major order. Relatedly, short write updates require fewer operations for data blocks located off the major data array diagonal.

Abstract: According to the present invention, after a test data pattern has been written to selected static memory cells, the wordlines of the memory cells are turned off and the bitline true and bitline complement of the memory cells are simultaneously pulled to a predetermined logic level for the duration of the long write test so that the memory cells are disturbed. After the long write test, the contents of the memory cells are read to determine which memory cells contain corrupted data and therefore have bitline to memory cell leakage problems.

Abstract: A method and a circuit device control insertion and storage of digital information in a memory and retrieval of the information from the memory. The method and circuit device ensure the digital information is correctly read out of the memory in the form of a number of coordinated bit positions, and the digital information is used to control one or several functions. The information intended to be inserted into the memory is given an address belonging to the memory. First control-sum-carrying bit positions are calculated from the bit positions of the digital information and their values coming into the memory according to a selected evaluation function. The bit positions of the digital information are stored in an address within the memory, and the first control-sum-carrying bit positions are stored in an address within a control memory.

Abstract: A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit.

Abstract: A process for testing a wrapped segment of a dual token ring transmits idle signals on the segment and monitors the received signals. If either an Active Monitor, Standby Monitor or Beacon frame is received the process loops. If a Ring Purge frame is received the process exits successfully and the segment is unwrapped. If a timer expires prior to the above, transmission shifts to a Claim Token frame. The process loops if a Beacon frame is received or if one of two timers expires. The process exits and the segment is unwrapped if a Ring purge frame is received or if n Claim Token frames are received having the hub source address.

Abstract: A method and an apparatus for monitoring and fault-analyzing a network which includes a plurality of LANs. LAN-to-LAN connectors are provided between LANs. The apparatus includes a monitor fault analyzer. A terminal is connected to a LAN, to issue a command which stores specific packets or transfers stored packets, from a command transmitter to LAN-to-LAN connectors. Upon receiving a command, a command holder of a routing unit (router) of the LAN-to-LAN connector holds the command. The router carries out the usual routing process to pass or block packets transferred from the LAN interfaces according to the addressee. A unit for detecting and copying the specified packets compares the address of each received packet with the addresses stored in the command holder, and if they agree with each other, copies the packet. A data storage unit stores the copy in the storage unit and the time of reception of the packet is measured by the timer and added to the packet.

Abstract: A clock signal hull detector includes a signal level monitor for detecting an extraordinary condition in which the clock signal to be monitored is stuck at either a high level or a low level and a turning point number monitor for detecting an extraordinary condition in which the clock signal changes its level between the high and low levels with high frequency. The outputs of the signal level monitor and the turning point number monitor are fed to a fault judgment portion, which delivers an output according to the extraordinary conditions. The output of the fault judgment portion is then fed to a counting portion at which a fault judgment signal is fed to its output when its input signal is counted to a predetermined value or above.

Abstract: A survival sequence register for a read channel employing a variable threshold peak qualification technique, has a first data shift register receiving a logic sum stream of two serial streams of coded digital data, corresponding to qualified peaks detected by a reading pick-up of positive and negative sign, respectively, and a pointer register. A control circuit generates an erase signal when an incoming pulse is recognized as corresponding to a detected peak of the same sign of the previously detected peak. The erase signal is input to logic gates which each drive a reset terminal of a flip-flop of the data shift register, with the exception of the first flip-flop of the register. The pointer register being reset when the control circuit receives a pulse corresponding to a peak of opposite polarity of the detected peak relative to the preceding pulse.

Abstract: A phase ambiguity removing device for determining the proper phase of the Pch, Qch data demodulated by a receive side demodulator of a Quadrature Phase Shift Keying (QPSK) system includes a second phase information controller for determining the most probable phase of the received signals when detection of synchronizing words fail in the Pch and Qch signals.

Abstract: A deinterleaver for reordering elements of an interleaved digital data sequence (data packet) to obtain an original digital data sequence. The deinterleaver is used in a mobile station operating in a mobile communication system. The interleaved digital data sequence is previously generated by interleaving elements of an original digital data sequence such that digital data elements located in successive positions of the original digital data sequence are located in positions separated by one or more intervening digital data elements in the interleaved digital data sequence.

Abstract: A variable-length decoder variable-length-decodes a received variable-length-encoded data. The variable-length-encoded data is bit-stuffed in each data block to create data portions with a predetermined number of bits. Frame start codes representing a start of each frame and mass of macroblock start codes distinguishing between a plurality of masses of macroblocks are inserted into the data. Synchronization of data between frames and masses of macroblocks are accomplished via: a first-in-first-out (FIFO) memory which stores encoded data; a decoder which variable-length-decodes the input data in response to a control signal and generates an end-of-block (EOB) error signal when an EOB is not found; a decoding interface which interfaces between the decoder and a timing controller; and a timing controller which synchronizes decoding by use of start and initialization signals.

Abstract: The invention provides a method of verifying the integrity of sequences of data transmitted from a first station to a second station in a broadcast network during a call set up between the first and second stations. First and second encipherment seals are calculated in a control station separate from and independent of the first and second stations, respectively in response to reception of a sequence corresponding to the transmitted data sequence and in response to reception of the sequence which is received in and retransmitted by the second station. A comparison of the calculated seals for integrity verification is preceded in the control station by searching for the first seal calculated according to an identification word of the sequence which is retransmitted by the second station. The invention relates to a method of verifying the integrity of data sequences exchanged between stations respectively belonging to different broadcast networks.

Abstract: For each of a plurality of modulation techniques, corresponding data reception history information is stored. A particular modulation technique is selected from amongst the plurality of modulation techniques (52). At least one block of data is transmitted using the particular modulation technique (55). A message is received that provides information regarding reception of the at least one block of data, including whether reception of each of the at least one block of data occurred without error (56). The data reception history information is updated for the particular modulation technique using the information regarding reception (57). The data reception history information is used to determine an estimate of transmission signal quality (51).

Abstract: A processing system intrusion and misuse detection system and method utilizes instructions for and steps of processing system inputs into events and processing the events with reference to a set of selectable misuses in a misuse engine to produce one or more misuse outputs. The system and method convert processing system generated inputs to events by establishing an event data structure that stores the event. The event data structure includes authentication information, subject information, and object information. Processing system audit trail records, system log file data, and system security state data are extracted from the processing system to form the event data structure. A signature data structure stores signatures that the misuse engine compares and matches to selectable misuses.

Abstract: In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected.

Abstract: A method and apparatus for detecting the presence or absence of errors caused along a designated section of a virtual path established within a communication network. The number of errors is detected at both the entrance and exit of a detection section. The number of errors detected at the entrance is transmitted to the exit by using a path overhead of a virtual path to be monitored, and the number of errors at the entrance is subtracted from the number of errors at the exit, thereby calculating the number of errors caused along the detection section. The path overhead containing data on the detected error count includes a parity compensation bit that is set so that the parity carried in the path overhead remains unchanged. This eliminates the need to recalculate bit interleave parity-2 for the virtual path under monitoring.