Abstract: Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Abstract: Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. This arrangement provides for the merged TAP and scan test port interfaces to be selected individually or in groups. Internal Tap Lock circuitry uses only the existing 1149.1 interface signals to produce a Lock Out signal to enable and disable a TMS/CS signal to the TAP circuitry.

Abstract: A reproducing method for a record medium includes the steps of performing a demodulating process for data that have been read from a record medium on which content data have been recorded, management information and additional information being embedded in the content data, the management information being with respect to a copy management, the additional information containing one of error detection code and error correction code added to the management information, detecting the additional information from a demodulated output signal, performing an error detecting process corresponding to one of the error detection code and the error correction code, and controlling an output operation for the demodulated output signal for the content data read from the record medium corresponding to the management information when no error is found in the error detecting process.

Abstract: A method of generating low density parity check codes for encoding data includes constructing a parity check matrix H from balanced incomplete block design (BIBD) in which a plurality B-sets which define the matrix have no more than one intersection point. The parity bits are then generated as a function of the constructed parity check matrix H.

Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columns 14 of an array of storage cells 16 which are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A method for selecting frame encoding parameters to improve transmission performance for a transmitting frame being transmitted from a transmitting station to a receiving station over a transmission medium of a frame-based communications network is provided, the transmitting frame having a header segment and a payload segment, the header segment being transmitted using a fixed set of encoding parameters such that the header segment can be received and decoded by all stations on the network, the payload segment being transmitted using a variable set of payload encoding parameters, the transmitting station sending the transmitting frame using one set of the variable set of payload encoding parameters at a time. The receiving station receives and decodes the header and payload segments of each transmitting frame. The decoding includes computing frame statistics. A plurality of sets from the variable set of payload encoding parameters are selected to form a possible set of payload encoding parameters.

Abstract: An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured.

Abstract: A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit. The failed functional block is then logically isolated from the remaining non-failing functional blocks. Scan testing of the remainder of the non-failing functional blocks then occurs to determine the integrity of the remainder of the integrated circuit. The data coming out of the failing functional block is not allowed into the other functional blocks as input data. The invention allows the integrated circuit to be used and sold at a reduced functionality for applications not requiring the failed functional block(s).

Abstract: A system and a method for forward error correction (FEC) which are efficient in terms of computational requirements and the amount of redundant information that must be transmitted. Given a set of input data transfer units (DTUs), to be sent from a transmitting device to a receiving device, the disclosed system uses prime numbers to generate subsets of the input DTUs. Subsets generated in this way are used to generate corresponding error correction DTUs by applying an XOR operation to all DTUs of the subset. The error correction DTUs are then appended to the input DTUs and transmitted to the receiver(s) as part of a burst. The error correction DTUs accordingly provide error correction information for data DTUs transmitted within a burst, and are used by receiving devices to restore data DTUs within the burst that were damaged or lost.

Abstract: A circuit for computing parity values is disclosed. The circuit includes a control decode unit. The control decode unit determines whether words received during a cycle correspond to more than one packet of data. The circuit includes a first parity processor. The first parity processor computes first parity sum values from first words associated with a first packet of data received during the cycle. The circuit includes a second parity processor. The second parity processor is capable of computing second parity sum values from second words associated with a second packet of data received during the cycle when the control decode unit determines that the data words correspond to more than one packet of data.

Abstract: Both link-level and path-level performance monitoring is obtained in any point of a multi-link network where transmitting points in the network are adapted to transmit codes only from a subset of the codes that receiving points in the network are adapted to receive, with one of the codes that transmitting points are adapted to transmit being chosen to represent an error-reporting code, and substituting, at monitoring points, any received code that is not one of the codes in the subset with the error-reporting code. By measuring the number of received codes that are in error, a link-level error measure is obtained, and by measuring the number of error-reporting codes, a path-level measure is obtained.

Abstract: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

Abstract: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is also configured to provide control information to the read logic. The control information includes a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information also includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information also includes the byte length size of the burst. The read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.

Abstract: A system and method for testing the data propagation time in an integrated circuit at relatively low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided with at least one inverter for sensing the feeding current of each circuit so as to obtain current pulses that are transformed into binary signals forwarded to a tester that measures the delay time between these signals.

Abstract: A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal, each IC having a plurality of data locations and comparing an output response at each data location with an expected value for the data location. The method also includes storing an address in a buffer for each data location where the response at the data location does not equal the expected value corresponding to the data location.

Abstract: An apparatus and method for increasing the data storage capacity of a data storage device 100 having media surfaces 23. One or more of a linear density of data, a track density of data, or an error code level of data, is selected for a portion 35 of a media surface 23. Data is recorded on the portion 35 of the media surface 23 at the selected linear density, track density, or error code level. Thereafter, the recorded data is read and an error rate of the recorded data is derived, directly or indirectly. The derived error rate is compared to an acceptable error rate, and if the derived error rate is greater than the acceptable error rate, the previous steps are repeated for another linear density, track density, or error code level, until the derived error rate is less than or equal to the acceptable error rate, to provide a recordable linear density, track density, or error code level of data for the media surface 23.

Abstract: A system and method for superimposing a sequence number of a packet into the CRC segment of the packet thereby allowing more bandwidth in the payload portion of the packet for carrying data is described. Also described is a method of acquiring additional information on the type of error in a packet, e.g., data transmission errors or sequence errors, from analyzing a CRC error. For example, a reported CRC error can be the result of the receipt of a packet with a sequence number the receiver is not expecting (which is a normal occurrence on transmission links due to transmitters resending packets that a receiver has already accepted) or can result from a real error in the transmission of a packet. A first error code check (CRC) value is calculated for the payload segment of a data packet. A second CRC value is calculated for the sequence number of the data packet. The first CRC value and the second CRC value are combined thereby creating a third CRC value.

Abstract: A method for analyzing test data for objects on an IC or a wafer is provided. The test data is linked to available layout information about the object under test. Certain objects are selected based on the test data. A representation of the selected objects is placed on a map of the IC or on a map of the wafer. The representation should correspond to the physical location of the object on the IC or wafer. Preferably, the representation comprises one or more polygons that enclose all devices that make up the object.