Abstract: Circuitry for performing a special test of an integrated memory circuit is disclosed, where the special test requires driving of both bitlines associated with a column of memory cells to a selected logic level, such as ground. The special test is performed in a mode different from normal operation of the memory, and is useful in performing a write disturb test, and in performing stress tests of memory elements such as pass transistors in static random access memory cells. The special test is performed by generating an internal signal selecting the placement of both bitlines in one or more bitline pairs to the selected logic level. Circuitry is also disclosed which uses the output enable terminal, in the special test mode, for controlling the driving of both bitlines to the selected logic level, as the output enable terminal otherwise has no required function in this special test mode.

Abstract: A method and system for capturing and controlling access to information in a data processing system is provided. The data processing system includes one or more operating systems coupled to a coupling facility. When one or more operating systems lose communication with the coupling facility, a surviving operating system captures some or all of the information in the coupling facility, including that information associated with the failed operating system(s). In order to capture the information when a system fails or at any other time, the information in the coupling facility is serialized, thereby preventing all access to the information except for those commands capturing the information. While the information is serialized, requests for the information are queued and then re-driven once serialization is released. If an operating system loses communication with the coupling facility during the creation of a dump, another operating system will continue the dump.

Abstract: A digital data reproducing circuit for use with a magnetic or optical data storage for detecting and flagging signal level drop-outs in pulse position modulated (PPM) recorded signal levels. Positive and negative peak amplitudes of a self-clocking PPM coded signal are compared to positive and negative valid information peak detectors to detect the clock and PPM data. Lower peak (in absolute terms) amplitudes that fall from the normal signal levels at the start of a drop-out and/or rise at the end of the drop-out, are detected by positive and negative drop-out peak detectors. The positive and negative drop-out peak detectors are inhibited when valid clock and data peak pulses are detected.

Abstract: A method and system for performing protection switching in a communications system is disclosed. The disclosed system and method include the ability to detect bit error burst conditions, in which data is highly errored over a brief time and responsive to which the protection switching procedure is not desired. The number of bit errors over a series of sample periods are counted, and the number of errors detected in each sample period is compared against a burst error threshold. A carryover value from the prior sample period (e.g., the number of detected errors above average) is preferably added to the detected errors in the current sample period prior to the comparison, so that error bursts are detected regardless of their alignment with the sample periods.

Abstract: An integrated circuit (IC) includes a functional module such as FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port on the integrated circuit is coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells, a test set of FLASH EPROM memory cells, and a port through which data in the array is accessible by external devices.

Abstract: A telecommunications operation support facility is arranged so that a user may easily build and/or update a program implementing a test strategy for testing a special services circuit without having to consider certain aspects that make the strategy complex. Such aspects include, inter alia, the configuration of the section of the special service circuit that is to be tested and the "vintage" of a remote test system which provides a way of accessing the section from a remote test point.

Abstract: A bit error measurement apparatus is capable of easily specifying pattern conditions which cause bit errors in an incoming signal pattern without measuring all of a test pattern by measuring a bit error rate at a selected position or region of a test pattern. The bit error measurement apparatus includes a test pattern generator which generates the test pattern for verifying the incoming signal to be tested, a verifier which receives the incoming signal and the test pattern and generates a bit error detection signal when the incoming signal and the test pattern disagree, a pattern position detector which detects a measurement region of the test pattern when receiving a synchronizing signal from the test pattern generator and generates a count enable signal corresponding to the detected measurement region, and an error counter which counts the bit error detection signal from the verifier based on the count enable signal from the pattern position detector.

Abstract: To a parity group including a plurality of data items and a parity code, at least two dummy data items are added to configure a logical group. The data items, dummy data items, and parity code of each logical group are written in mutually different disk drives. When renewing a data item of a parity group, an old data item and an old parity code are read from the associated drives so as to renew the old data item. According to a new data item for the renewal and the old data item and parity code, there is created a new parity code. The new parity code is written in one of the drives containing dummy data items available at an earliest point of time for the write operation. Prior to the write operation of the new parity code, the new data item is written in a drive containing another dummy data item.

Abstract: In a communication system (10), a receiving node (14) estimates bit error rate (BER) and the accuracy of the BER estimate based upon a single burst of a data communication signal (12). An appropriate decision rule (92) is selected (90) in response to the BER accuracy estimate. Different decision rules (92) are available to bias different decisions to favor desired outcomes. The bias is configured in response to the BER accuracy estimate. The selected decision rule (92) is evaluated (96) in view of an estimated BER. In response to this evaluation, a transmitting node (14) may be instructed (104) to increase or decrease its transmit power level. In addition, the BER may be measured, and the measurement used to verify the appropriateness of the decision rules (92).

Abstract: The method provided first partitions the memory, which has defective cells at unknown locations, into a plurality of frames. Each of the plurality of frames has a corresponding N-bit of cell, and M-bit of cell for storing an index representative of the defectiveness of the (M+N)-bit cell. Secondly, the method performs a predetermined pattern write-read access test to the corresponding (M+N)-bit cell for each frame to determine if the (M+N)-bit of cell is defective. Thirdly, the method stores a first value of the index into the corresponding M-bit of cell for each frame, if the (M+N)-bit cell is good. Fourthly, the method stores a second value of the index into the corresponding M-bit of cell, if the (M+N)-bit cell is defective.

Abstract: A transmission test apparatus having a system-clock redundancy system for testing a transmission path is proposed. In the transmission test apparatus, a clock switching unit selects a proper one from a plurality of system clocks in response to a clock selection signal and supplies a selected system clock. A test-signal check unit performs a synchronization operation in which a first test pattern generated based on the selected system clock is synchronized with a test signal coming through the transmission path and compares the first test pattern with the test signal. A synchronization detection unit detects the synchronization between the first test pattern and the test signal by examining the comparison result of the test-signal check unit to produce a synchronization detection signal. An error counter performs a counting operation in which a number of unidentified bits is counted as error bits after receiving the synchronization detection signal.

Abstract: A method of and apparatus for decoding data from positive and negative pulses of an encoded pulse train, e.g. a NRZ pulse train for PPM encoding, wherein the recorded data is subject to drop-outs and drop-ins. Data bits are decoded from valid positive and negative pulses exceeding positive and negative peak pulse thresholds. Drop-outs are identified in the encoded pulse train as a function of read out positive and negative pulse magnitudes not exceeding positive and negative thresholds, and drop-out flags are provided in lieu of the respective positive and negative pulses. Decoded data bit signs are stored in memory locations, and drop-out flags are stored in memory locations in relation to the stored data bit signs such that the beginning and/or end of a drop-out in the encoded pulse train is indicated. Drop-out flags are also stored in response to the occurrence of two successive valid positive pulses or two successive valid negative pulses in the pulse train.

Abstract: A method of verifying the baud rate for communication of data by an Asynchronous serial device residing within a data processing system. The data processing system having a first Asynchronous serial device and a second Asynchronous serial device. The first and second serial devices are connected one to another for communication of data therebetween. The first and second serial devices are initialized with a common baud rate for transmission and reception of data, respectively. A test sequence pattern is created, and transmitted at the common baud rate from the first serial device to the second serial device. The second serial device transmits the received test sequence pattern back to the first serial device. The test sequence pattern is then verified as either valid or invalid.

Abstract: A computer system determines the presence of a device attached to a system bus that responds to I/O or memory reads by driving the data lines of that bus to values normally present on an undriven bus. The data bus is first driven to a value other than its undriven value, such as to 00h. Then, circuitry measures the time it takes on an I/O or memory read for the data bus to return to its normally undriven value. If the response time is less than the time it takes for an undriven data bus to return to its undriven state, then an expansion board is driving the data bus to its normally undriven value. This indicates that the expansion board is responding to an I/O or memory read on the data bus, even though it is responding by driving that bus to its normally undriven value. Further, by determining the maximum response time of a device, system performance is then improved by tuning cycle time to correspond to that maximum response time.

Abstract: A device (1) for determining whether a maintenance message generated during an operating cycle of a system by a maintenance device (2) monitoring the system is or is not representative of a real fault in the system. The device (1) includes a comparator (D) which compares a short-term occurrence rate of the message to a long-term occurrence rate of the message, for each maintenance message generated, and determining whether the message is or is not representative of a real fault. The occurrence rates are calculated by a computer (CAL) on the basis of information contained in memories (M1, M2, MN) and indicate the presence or non-presence of the message in the course of predicting cycles.

Abstract: The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.

Abstract: A method of determining an error level of a data channel comprised of (a) receiving channel parity error data indicating when bit errors occur within a set of data carried on the channel (channel error events), successively integrating the channel error events data over successive accumulation periods, comparing the integrated channel error events data with a threshold, and indicating an alarm in the event the integrated channel error events data exceeds the threshold.

Abstract: A test data pattern, an address pattern and a control signal are applied to a memory under test (MUT) from a pattern generator (2). Data read out of the memory under test and expected data are compared by a logic comparator (4), which outputs a comparison signal indicating PASS or FAIL depending upon they match or not. When the logic comparator detect the match, the comparison signal is held in a register (42), from which it is outputted as an inhibit signal. The inhibit signal is applied to an inhibit gate (44) to cause it to inhibit the passage therethrough of a write enable signal to the memory under test, thereby preventing an excessive write in the memory.

Abstract: A computer system includes error handling hardware and software that logs the source of application program or system software errors before a reset occurs. Upon a catastrophic error, a retriggerable timer, which is periodically retriggered during normal system operation, instead times out causing a hardware reset. A predetermined time before this retriggerable timer times out, however, the microprocessor in the computer system is interrupted, and executes an interrupt routine in which it determines that the retriggerable timer is about to timeout, and logs the currently executing applications program or currently executing point in system software, as well as the actual location within the applications program or the system software. The reset subsequently occurs, but not before this information valuable for debugging and diagnosis is logged.

Abstract: In a method and apparatus for selective convolutional interleaving or de-interleaving of symbols or data bits, a plurality of segments are defined in random access memory, with each segment including a different number of locations for storing symbols. Previously stored symbols are sequentially read out of current locations in the segments respectively, and new symbols are read into the current locations. Next locations in the segments are redesignated as current locations respectively, and the operation is repeated until all of the symbols have been interleaved or de-interleaved. The first location in each segment is designated by a respective segment pointer. The current and next locations are designated as relative offset pointers from the segment pointers, and these locations are incremented by incrementing the offset pointers. Interleaving or de-interleaving operation is determined by the direction in which the segments are sequentially selected for the read/write operations.