Abstract: A diagnostic system for finding failures in an integrated circuit includes a scan-chain circuit which is comprised of a plurality of flip-flop circuits electrically connected in series to one another and outputs logic data stored in the flip-flop circuits on receipt of a control signal. The diagnostic system includes (a) a first identifier which identifies a circuit group which is suspected to have failure therein, among circuit groups surrounded by the scan-chain circuit, (b) a first extractor which extracts logic data of an input terminal of the circuit group having been identified by the first identifier, (c) a second extractor which extracts logic data to be input into each of fundamental logic circuits constituting the circuit group, and (d) a second identifier which identifies a fundamental logic circuit suspected to have failure therein by comparing the logic data having been extracted by the second extractor, to one another.

Abstract: A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device.

Abstract: Data from a host computer is buffered, transferred to a logical formatter, compressed and converted to a format suitable for storage on a magnetic tape before being arranged and written sequentially into a main buffer where parity bytes are added as each row of a dataset is written. A physical formatter takes the data sequentially from the main buffer and writes them as codeword quadsets in plural tape tracks. A determination of whether each codeword quadset is acceptably recorded is made by evaluating each codeword quadset for header and codeword quadset pair errors and combining the evaluations.

Abstract: A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped.

Abstract: Estimation of symbols related to each other by a parity relationship previously created by an encoder, is effected by a function having several components effecting a calculation of probabilities corresponding to a state of the encoder. The probabilities are of a first type, resulting from the observation of the effects of the previous states of the encoder on the current state, of a second type, resulting from the observation of the effects of the subsequent states of the encoder on the current state, and of a third type, representing the belonging of a symbol to a predetermined part of an encoding alphabet. A specific multiplexer is controlled by a state machine and cooperates with a calculator so that not only the probabilities of the first and second types but also the probabilities of the third type are obtained by one and the same circuit.

Abstract: A method for processing a received communication which includes periodic transmissions of a set of information segments. A first transmission of the set of information segments is received and processed to identify each of the segments as valid or invalid. The valid segments of the first set are then stored. Where all segments of the set are not stored, subsequent transmissions of the set of information segments are received and only those segments not previously stored are processed to identify each such segment as valid or invalid. The valid segments so identified are then stored. Subsequent transmissions are repeatedly received unless all segments of the set have been stored.

Abstract: A system and improved method are provided for storage and error recovery of streams of MPEG data on storage media in audio/visual systems. Storage locations on the storage media are selected for streams of MPEG data according to the data rates of the streams of MPEG data and the properties of the available storage locations on the storage media. Error recovery is selectively implemented based on the content of the streams of MPEG data, and transmission bandwidth of the streams of MPEG data is maximized.

Abstract: The invention discloses a method and apparatus for time stamping data packets under controlled conditions. Embodiments of the invention eliminate or minimize the error, caused in existing applications, by the elapsed time between the moment of a data packet generation and a the transmission of the data packet. Embodiments of the invention insert an initial data value, in lieu of the time stamp, into the data packet. Embodiments of the invention delay time stamp insertion to just prior to data transmission. A time stamp is inserted in time stamp location, and using a set of correction equations, embodiments of the invention generate a final error checking value that is attached to the data packet. Embodiments of the invention insert a precision time stamp into the data packet and apply a correction to the error checking value. At the end of the processing of the data packet, the latter contains a time stamp that has been introduced with a high precision, and has a correct error checking value.

Abstract: A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a “fail” bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also includes a set of programmable area fail counters, each for counting of the number of memory cells within a separately selected area of the memory's address space. After the test, the computer processes the counts to determine whether it needs to allocate the spare rows and columns and, in some cases, to determine how to allocate the spare rows and columns.

Abstract: The present invention provides a method for operating a TAP controller having a first input terminal (Etms) for inputting a logic test mode selection signal (tms) and a second input terminal (Etrst) for inputting a logic reset signal (trst); the TAP controller being configured in such a way that it is in a test mode if the test mode selection signal (tms) has a first logic state (“0”), and it is in no test mode if the test mode selection signal (tms) has a second logic state (“1”), that it can be reset asynchronously by single application of the logic reset signal (trst) from the first logic state (“0”); the method having the following steps: provision of an external logic reset signal (reset_n): formation of a logic ORing of the external logic reset signal (reset_n) and the inverted logic test mode selection signal (tms) for the generation of the logic reset signal (trst); and application of the logic reset signal (trst) generated by the logic ORing to the second input terminal (Etrst).

Abstract: A semiconductor chip of the present invention includes a plurality of first elements each of which diagnoses itself, and a second element which inputs diagnosis results from the first elements and determines whether or not there is a faulty first element in the first elements. A method of the present invention which is performed in a semiconductor chip including a plurality of first elements, includes diagnosing the first elements by itself; and determining whether or not there is a faulty first element in the first elements based on diagnosis results from the first elements.

Abstract: A photolithography system includes a photolithography tool 32 that includes a stage upon which a semiconductor wafer is mounted. The tool is operable to move the stage to automatically focus a pre-determined image on a surface of the semiconductor wafer. The tool is further operable to log movements of the stage. The system also includes an automation host computer 36 operable to poll the photolithography tool 32 to obtain data reflecting the logged movements of the stage. The automation host computer 36 is further operable to analyze the data and compare the data to pre-determined error conditions. The host computer also takes a pre-determined action, including sending an electronic mail message to the personal computers 38 of relevant line personnel, in the event the data meets the pre-determined error conditions.

Abstract: A data transfer system providing parity uses a method and apparatus for transmitting a data clocking signal in a parity bit location along a data bus to latch an accompanying data byte at a receiving device. A transmitting device, coupled to the receiving device through the data bus, generates a data clock signal and latches the clock signal into the parity bit location of the data bus. The clock signal and data byte are then transmitted along the data bus to the receiving device. The receiving device uses the clock signal to latch the data byte from the data bus. Thus, the data transfer system uses the data clock signal transmitted in the parity bit location of the data bus to validate and synchronize the accompanying data byte at the receiving device.

Abstract: A method for identifying an error condition due to a faulty cable connection in a network comprising a plurality of computer systems, at least one of the computer systems including a network adapter with the network adapter including a media access control (MAC) unit, includes initializing a plurality of mechanisms for tracking a plurality of conditions in the MAC of the network adapter. The method further includes receiving a transmit demand request in the network adapter and updating the plurality of mechanisms according to a current status of each of the plurality of conditions. In addition, the method includes determining whether a predetermined threshold has been reached in one or more of the plurality of mechanisms, wherein when one or more of the plurality of mechanisms has reached the predetermined threshold, a faulty cable connection is identified. In a system aspect, the system includes a plurality of counting mechanism for tracking each of a plurality of error conditions.

Abstract: A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values.

Abstract: A device for the serial transmission of data between at least two terminals which are interconnected via a two-wire line. Each terminal has a bus-coupling circuit having at least one transmitting section or one receiving section. The transmitting section has at least two driver circuits which are each connected to one line of the two-wire line. A resistor network is switched between each driver circuit and line. During a data transmission, the transmitting section transmits complementary signals to the lines. The receiving section has a comparator which is connected at its one input to a line of the two-wire line and which is supplied at its second input with a specific reference potential. The output signals from the comparators are evaluated by an evaluation circuit. The reference potentials of the comparators and the resistor networks are designed to allow both comparators to emit a switching signal, in dependence upon the transmitted bit conditions, in the case of an error-free operation.

Abstract: In a fault-tolerant distributed file system, the server state needs to be reconstructed after the server restarts or when its function is taken over by another node. A crucial part of the server state is determining whether or not in-flight, directory-operations initiated by the clients have been completed. Described is a check-before-request scheme that solves this problem. A global lock is obtained on the directory or directories first. A check is made on the directories to see if the operation would succeed, and if so a request is made to the server for the operation. If the server were to fail during the execution of the operation, completion of the operation prior to failure can be determined by merely re-examining the directory contents.

Abstract: A multiplexed system including at least two microcomputers operable in parallel with each other, and watch dog timers. One of the watch dog timers is connected for receipt of an input signal from one of the microcomputers to check a program run-away condition in the one microcomputer. The other watch dog timer is connected for receipt of an input signal from the other microcomputer to check a program run-away condition in the other microcomputer. The one microcomputer checks the other watch dog timer, and the other microcomputer checks the one watch dog time. Calculation results are fed from the respective microcomputers to a comparator circuit which produces an output signal from the multiplexed system. When the one microcomputer checks the other watch dog timer, the input signal from the other microcomputer to the other watch dog timer is interrupted. The other watch dog timer is checked based on an operating condition of the other microcomputer.

Abstract: Apparatus and methods for distributing synchronization throughout a network is disclosed. The distribution of the synchronization is through the use of generating a reference timing signal, and by counting the line clock pulses between the start of a frame and the timing reference signal pulse at a first office and that count is then encoded and transmitted to the next office. At the next office, the transmitted count is decoded and used for regenerating synchronization by counting a number of received line clock pulses from the start of the frame to regenerate the reference timing signal. Particular criteria for selecting the frequencies for the timing reference signal are disclosed.

Abstract: Interleaving/de-interleaving of data is achieved by storing and subsequently retrieving portions of the data from circular buffers (60,70). The circular buffers (60,70) are addressed such that each circular buffer corresponds to an index of data (B.sub.i). Thus, data (80) is written into a circular buffer (60,70) using a first modulo scheme and read using a second modulo scheme, where the second modulo scheme is based on the interleaving scheme. An index array (20) is used to point to the appropriate entry in the circular buffers(60,70) to ensure a proper interleave/de-interleave process.