Abstract: An integrated test core for mixed-signal circuits comprises a periodic waveform generator capable of generating arbitrary band-limited waveforms for excitation purposes and a waveform digitizer for extracting an arbitrary waveform from the test circuit's analog response signal. The digitized response may be tested and measured using DSP techniques. Preferably, the waveform generator and digitizer are synchronously controlled. The core is a nearly all digital implementation with the exception of a reconstruction filter (optional) for sending the test signal to the circuit under test (CUT) and the comparator for extracting the digitized waveform from the CUT's response. The periodic waveform generator may comprise a ?? modulator and, optionally, a reconstruction filter between the modulator and CUT.

Abstract: The configuration of a microcomputer to be used as the control device of a medium reading apparatus is such that writing unit by unit into and erasion block by block from a prescribed area, such as a user data storage area, in a nonvolatile memory built into the microcomputer makes possible, if any writing into the user data storage area is needed, for data to be successively written while updating the units, data included in the prescribed area to be erased when all the units have been written into, and the next data to be written into the erased blocks.

Abstract: A structure and method for translating address buffer coordinates for a device under test having two or more similar repeatable units. The method comprises identifying a repeatable unit of the repeatable units, preparing a look up table for translating buffer coordinates of a reference unit of the repeatable units and displacing information from the look up table to correspond to the repeatable units.

Abstract: The invention proposes a mechanism for retransmitting packets which comprises a step for checking at the transmitter whether the retransmitted packet will be received by the receiver in time to be processed. To this end, the receiver sends in its retransmission request the processing time indication of the packet being processed at the receiver when the request is transmitted. At the transmitter end, this processing time indication is compared with the processing time indication of the packet to be retransmitted so as to authorize or block its retransmission.

Abstract: Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated from the generator function. A set of check matrix columns is generated, where each check matrix column includes a matrix having a subset of the set of primitive elements. A check matrix is generated from a subset of the set of check matrix columns, where the check matrix yields a syndrome that comprises an error pattern for the word. The check matrix is reported.

Abstract: An error rate detector is provided. The error rate detector includes a sequence generator that is adapted to generate a test sequence for comparison with a received sequence. The error rate detector also includes a self synchronization circuit that is responsive to the test sequence received from the sequence generator and the received sequence. The self synchronization circuit is adapted to move the sequence generator to a different point in the sequence based on a measure of mismatches between the test sequence and the received sequence.

Abstract: An encoder (10,30) and method for encoding data comprising a pseudo random number generator (12) for generating an array of pseudo random numbers (15), and calculating means (10,30) for calculating a checkword (11,23,25) using the array of pseudo random numbers generated and a data sequence provided by a data unit (13).

Abstract: A highly reliable industrial control system is produced using a network running a standard serial protocol on two redundant messages. A safety protocol is embedded within the standard serial protocol by adding to special error detecting data redundant with the protocol of the standard serial network. In addition, only a single network protocol module (CAN) is necessary to transfer two logical messages of data between modules. In order to still provide redundancy, the data on one of the messages is encoded in a predetermined manner, such as by inverting each bit of data, prior to transmission over the network. The data is then decoded at the destination module and compared to the data on the other logical message to determine whether a transmission error has occurred. Safety protocol may be implemented in an additional level for integrated circuits or through firmware changes in programmable aspects of the industrial controller components.

Abstract: A method and circuitry for ensuring proper connections of a multi-wired cable bridging two electrical components in a programmable logic controller (PLC) system. The method involves: generating a pre-specified voltage level when the cable is properly connected, testing for the existence of this pre-specified voltage level, and generating an error signal if the pre-specified voltage level is not detected. The error signal generated by a component causes the component to electronically switch off its data connection via the multi-wired cable with the other component, and may cause the component to reset itself.

Abstract: The invention is to provide a method for communicating data between a digital camera and a portable electronic communication device comprising the processes of transmitting an instruction packet created by the electronic communication device to the digital camera for storage by means of a defined image data protocol; converting image data stored in the digital camera into at least one reply packet based on the instruction packet by performing the image data protocol by the digital camera and transmitting the reply packet back to the electronic communication device; and performing an error checking on at least one check field of the reply packet by the electronic communication device by means of the image data protocol so as to ensure that no erroneous image data being received.

Abstract: A system and method that selects an encoder redundancy scheme based on the projected cost of concealing the errors using an anticipated error concealment strategy. The invention provides a system for encoding a data set, comprising: a system that anticipates an error concealment strategy that will be used by a decoder in the event that the data set contains errors when received by the decoder; an analysis system that projects a cost for concealing the errors using the error concealment strategy; and a system that selects a redundancy scheme for encoding the data set based on the projected cost of concealing the errors using the error concealment strategy. Also provided is a decoder system for decoding packets of data, comprising: at least one error concealment strategy for concealing errors in an erroneously received packet of data; and a feedback system that provides feedback information regarding the error concealment strategy used by the decoder system to conceal the errors.

Abstract: A system and method for an election and data majority mechanism that solves problems such as bit flipping, mistracking, miscaching, and I/O status errors during real-time operations. Multiple copies of data are stored on various storage media of a data processing system. Errors that occur on the storage media or on other components of the data processing system are resolved by selecting the data with the highest frequency as the data majority. The data majority is propagated throughout the storage media to correct errors.

Abstract: A row of the data block which is a set of the data sector is distributed to constitute two blocks. In this case, as a distribution condition, an even-number row block of the even-number sector and the odd-number row block of the even-number sector, the odd-number row block of the even-number sector and an even-number row block of the even-number sector are obtained. Then, the block is aggregated in the transmission order, and an outer parity is scattered to each sector to form an interleaved form.

Abstract: A control direction circuit (24) provides at least one of code error information and code error correction information on a transmission signal for which compensation has been performed by a plurality of compensation circuits (20a through 20e), to respective ones of the plurality of compensation circuits. Thus, the control direction circuit (24) controls each of the compensation circuits individually based on the thus-provided at least one of the code error information and code error correction information so as to compensate the waveform degradation on the transmission signal.

Abstract: An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the integrated circuit includes a disabling device coupled thereto between the input/output terminal and the output driver of the respective input/output terminal. A DRAM module is disclosed having a plurality of partially good DRAM devices wherein the known bad input/output terminals are permanently disconnected using a disabling device, both the known good and known bad input/output terminals being coupled to conductive traces of a carrier substrate.

Abstract: The preferred embodiments described herein provide a method for altering a word stored in a write-once memory device. In one preferred embodiment, a write-once memory device is provided storing a word comprising a plurality of data bits and a plurality of syndrome bits. The word is altered by identifying X bit(s) in the word that are in an un-programmed state and switching the X bit(s) from the un-programmed state to a programmed state, where X is sufficient to introduce an uncorrectable error in the word. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.

Abstract: The invention creates a method for testing circuit units (100) to be tested, in which test output signals (107a-107n) can be combined, where test input signals (106a-106n) are input from a test device (105) into the circuit unit (100) to be tested via a connecting unit (104), the circuit unit (100) to be tested is tested by means of the test input signals (106a-106n) in order to obtain corresponding test output signals (107a-107n) which indicate an operability of the circuit unit (100) to be tested, a gate unit (101) is connected to the connecting unit (104) by means of a first test mode switching unit (102) and of a second test mode switching unit (103), in such a manner that the test output signals (107a-107n), after being logically combined in the gate unit (101), are provided as a combined test output signal (109) via a single output line (110), and the combined test output signal (109) is output to the test device (105).

Abstract: A receiver including a signal reception unit, for receiving a signal from a dynamically fading channel, a demodulator, connected to the signal reception unit, for demodulating the received signal, thereby producing a demodulated signal therefrom, a quantizing processor, connected to the demodulator and to the signal reception unit, for analyzing the received signal and for quantizing the demodulated signal, thereby producing a quantized signal, and a decoder, connected to the quantizing processor, for decoding the quantized signal, wherein the quantizing processor normalizes the demodulated signal according to the estimated fading of the received signal.

Abstract: A test circuit for testing a first memory including a plurality of memory cells includes a first address decoder couplable to the first memory, the first address decoder configured for receiving a first input address and generating a first signal in response thereto for selectively accessing one or more of the memory cells in the first memory. The test circuit further includes a second memory including a plurality of memory cells and a second address decoder couplable to the second memory, the second address decoder configured for receiving a second input address and generating a second signal in response thereto for selectively accessing one or more of the memory cells in the second memory array.