Patents Examined by R. R. Kucia
  • Multi-layer electric circuit board and blanks therefor
    Patent number: 4524239
    Abstract: A multi-layer blank for an electrical circuit board has at least one internal layer, which may constitute a common power supply or ground plane. The inner layer consists of an electrically conductive network extending throughout the area of the inner layer and formed by the repetition of an elementary predetermined pattern in two orthogonal directions. The elementary pattern has such a shape that adjacent patterns are in electrical contact so that the network is equipotential. The pattern is also of such a shape that there is formed a first regular grid of predetermined pitch p whose nodes constitute insulated sites and a second grid off-set by p/2 from the first grid in at least one of the orthogonal directions. The second grid has the same pitch p as the first one and has nodes one at least of which per elementary pattern is insulated while the other ones belong to the conducting network.
    Type: Grant
    Filed: August 31, 1982
    Date of Patent: June 18, 1985
    Inventor: Francois Rouge
  • Universal circuit prototyping board
    Patent number: 4524240
    Abstract: A universal multilayer circuit prototyping board is provided having a predefined universal pattern of socket pin perforations which accommodates all standard DIP integrated circuit packages at virtually any position on the board. The universal board allows high density circuit packing while maintaining excellent electrical performance with high speed circuits.
    Type: Grant
    Filed: August 17, 1983
    Date of Patent: June 18, 1985
    Assignee: Lucasfilm Ltd.
    Inventors: Rodney D. Stock, Gary H. Newman
  • Matrix board
    Patent number: 4522449
    Abstract: A novel electrical interconnection system is described. The system includes a novel multiple-bussed matrix board and associated hardware and assembly tools for use therewith. The matrix board includes a plurality of plated-through holes arranged in a coordinate system of rows spaced 0.100 inches on center, measured from aperture-to-aperture. Selected apertures are electrically connected to selected bus bars on one or the other side of the board.
    Type: Grant
    Filed: November 14, 1983
    Date of Patent: June 11, 1985
    Inventor: C. Michael Hayward
  • Multi-layer conductor plate and a method of making
    Patent number: 4520228
    Abstract: A multi-layer conductor plate consists of a copper-clad base plate (1) on which a first layer of conductor paths (2,3,4; 5,6,7) is formed by applying an etch-resistant, electrically conductive varnish at the respective locations. The copper layers not covered by the etch-resistant varnish are removed by etching in etching bath. Subsequently an insulating varnish layer (16) is applied at least in the area of intersections of conductor paths of the first layer and a second layer. A varnish adapted to be galvanized and preferably being carbonaceous is applied at predetermined locations and subsequently coated with a metal layer applied galvanically.
    Type: Grant
    Filed: August 24, 1982
    Date of Patent: May 28, 1985
    Assignee: Wilhelm Ruf KG
    Inventor: Horst Hoffmann
  • Printed circuit board card cage
    Patent number: 4519016
    Abstract: A dual density printed circuit board card cage for housing a plurality of printed circuit board cards in a parallel, stacked relationship. The card cage embodies a unique, intermediate frame member comprising a single piece of sheet metal having a plurality of openings and guide means on opposite sides of the intermediate frame member for mating with corresponding guide means on the upper and lower frame members. The guide means are comprised of a plurality of web portions each including a pair of guide edges extending upwardly and downwardly and in an alternating pattern.
    Type: Grant
    Filed: September 29, 1983
    Date of Patent: May 21, 1985
    Assignee: Magnetic Controls Company
    Inventors: James D. Bradley, Gregg B. Amundson
  • Underwater electrode with waterproof integrity
    Patent number: 4517440
    Abstract: An electrode for use in cutting or gouging workpieces underwater by means of an electric arc comprising a generally elongated porous substrate, with a circumferential recess proximate one end to form a snap-off end on the substrate. The substrate is covered with a combined electrical insulating and waterproof coating except for a portion of the end opposite the recess which is inserted into a suitable underwater torch. When the electrode is submerged it has complete waterproof integrity until the snap-off end is removed to allow the substrate to be brought in contact with the workpiece so that an arc may be struck and maintained between the substrate and the workpiece to achieve cutting or gouging.
    Type: Grant
    Filed: February 22, 1980
    Date of Patent: May 14, 1985
    Assignee: Arcair Company
    Inventors: Raymond L. Sadauskas, Paul E. Moore
  • Circuit board housing with zero insertion force connector
    Patent number: 4517625
    Abstract: The invention is a circuit board housing for electrically coupling at least one circuit board 14 to a mother board 20 mounted within the housing 10, the circuit board 14 having a plurality of first electrical terminals 90 mounted along an edge portion thereof. The housing has at least one zero insertion force socket 12 wherein a plurality of second electrical terminals 18 are mounted therein. An electrical connector 16 is provided to couple the printed circuit board 14 to the mother board 20. The electrical connector 16 comprises a circuit board support member 26 slideably engageable with the socket 12. A pair of jaws 40a and 40b are attached to the support member 26 which are adapted to releaseably engage the edge portion of the circuit board 14. The electrical connector further comprises first and second resilient pads 62 and 63 mounted within the jaws.
    Type: Grant
    Filed: November 9, 1983
    Date of Patent: May 14, 1985
    Assignee: Lockheed Corporation
    Inventors: Attila Frink, Robert A. Morrison
  • Method of manufacturing an identification card and an identification manufactured, by this method
    Patent number: 4514785
    Abstract: An identification card with an integrated semiconductor circuit (13) which is mounted on a secondary carrier (11) and which is electrically connected to conductor patterns (3, 5) on both sides of the secondary carrier (11). The secondary carrier (11) is mounted in a primary carrier (29) together with the integrated semiconductor circuit (13). The secondary carrier (11) comprises a plated-through hole (7) which is partly removed in order to form a recess (15) in the secondary carrier (11) in which the semiconductor circuit (13) is accommodated. The semiconductor circuit (13) is electrically connected, by means of connection wires (23, 25), to a conductor pattern (3) on the secondary carrier (11) and, also using an electrically conductive glue (21) and the metal hole plating (18) of the remainder (17) of the plate-through hole (7), to the other conductor pattern (5) on the secondary carrier (11).
    Type: Grant
    Filed: April 23, 1984
    Date of Patent: April 30, 1985
    Assignee: U.S. Philips Corporation
    Inventor: Paul Parmentier
  • Connection of leadless integrated circuit package to a circuit board
    Patent number: 4513353
    Abstract: A device for connecting leadless integrated circuit packages to a chip carrier housing or socket and then to a printed circuit board is taught. Briefly stated, a mask is selectively disposed on a printed circuit board. Locating ribs are correspondently disposed on a chip carrier housing so as to cooperatively engage the slots created by the absence of the mask on the printed circuit board. Additionally, barriers for separating contacts contained in the chip carrier housing are maintained at the interior and the exterior portion of the chip carrier housing walls with no material disposed therebetween thereby minimizing capacitive as well as inductive effects which may come about.
    Type: Grant
    Filed: December 27, 1982
    Date of Patent: April 23, 1985
    Assignee: AMP Incorporated
    Inventors: Johannes C. W. Bakermans, Dimitry G. Grabbe, Iosif Korsunsky
  • Backpanel assemblies
    Patent number: 4511950
    Abstract: Each printed circuit board (PCB) on a backpanel has an associated set of power supply studs and power supply pins at an edge of the backpanel. The PCBs can be powered commonly via power supply buses interconnecting the studs. Alternatively, the PCBs can be powered individually via respective power supply PCBs which are inserted into connectors formed partly by the power supply pins and partly by pins on an additional, power supply, backpanel which is mounted to extend contiguously from and in the same plane as the first backpanel. The two arrangements can be combined to power groups of PCBs individually with all of the PCBs in each group being powered commonly.
    Type: Grant
    Filed: June 27, 1983
    Date of Patent: April 16, 1985
    Assignee: Northern Telecom Limited
    Inventors: Charles B. D. Bunner, David S. Brombal
  • Circuit board fabrication leading to increased capacity
    Patent number: 4511757
    Abstract: Printed circuit boards having a plurality of circuit layers are produced on a copper-clad substrate by first forming a pattern in a desired configuration to produce the first layer of the printed circuit board, then covering it with an energy-sensitive material comprising a rubber modified epoxy resin, an acrylated epoxy resin and a viscosity modifier; the energy-sensitive material is delineated in a desired pattern and developed to uncover portions of the underlying metallization pattern and the entire substrate is then blanket cured to produce a rigid layer having openings in appropriate places; the openings are metallized and a second copper pattern is produced on the cured polymer by conventional metallization and lithographic techniques. If desired, the process is repeated until a suitable number of copper patterned levels are obtained.
    Type: Grant
    Filed: July 13, 1983
    Date of Patent: April 16, 1985
    Assignee: AT&T Technologies, Inc.
    Inventors: Jose A. Ors, Richard D. Small, Jr.
  • Formation of narrow conductive paths on a substrate
    Patent number: 4510347
    Abstract: A method of forming electrically conductive paths within grooves formed in a substrate wherein the width of the grooves is of the same order of magnitude as the thickness of an electrically conductive layer deposited on the substrate and in the grooves. The substrate with grooves therein is exposed to a medium whereby electrically conductive material from the medium deposits substantially uniformly on all surfaces of the substrate which are exposed to the medium. In this way, the build-up of conductive material in grooves will take place along the side walls as well as the bottom of the grooves. If the layer is of substantially the same order of magnitude as the width of the groove (about one half the groove width or greater), the grooves will fill up with conductive material. The remainder of the substrate will ultimately provide a substantially flat conductive layer on the substrate surface.
    Type: Grant
    Filed: December 6, 1982
    Date of Patent: April 9, 1985
    Assignee: Fine Particles Technology Corporation
    Inventor: Raymond E. Wiech, Jr.
  • Device for housing communication circuits and equipment
    Patent number: 4510552
    Abstract: A housing device for housing communication circuits and equipment which includes a frame which can receive a plurality of printed boards, each printed board comprising a communication circuit and circuit cables disposed along the frame. A test jack testing the circuit is disposed at the front end of each printed board, and a connector, which is connected to a connector mounted on the frame, disposed at the rear end of the printed board. The test jack includes further includes first and second leads within a molded body, the opening of each jack being disposed at the front side of the printed board so that the insertion direction is parallel with the printed board. The first and second loads are formed so that they contact each other in the neck of the jack, separate from each other at the rear side of the jack, and project out of said molded body.
    Type: Grant
    Filed: November 18, 1982
    Date of Patent: April 9, 1985
    Assignee: Fujitsu Limited
    Inventors: Takashi Kanno, Akira Oka, Ituo Okamoto, Kouji Mizushima, Shinji Oguro
  • Leadless integrated circuit package housing having means for contact replacement
    Patent number: 4504887
    Abstract: A high speed socket housing having a relatively simple manner of contact inspection and/or replacement is taught. Briefly stated, the device includes a chip carrier housing having a portion which is removable therefrom and which thereby exposes the contacts contained in slots or partitions in the housing. Thereby, upon removal of a portion of the housing an inspection, replacement, and/or testing of individual contacts may be accomplished without disturbing the remainder of the contacts or removal of the entire chip carrier housing from a printed circuit board.
    Type: Grant
    Filed: April 1, 1983
    Date of Patent: March 12, 1985
    Assignee: AMP Incorporated
    Inventors: Johannes C. W. Bakermans, Iosif Korsunsky
  • High-speed, high pin-out LSI chip package
    Patent number: 4498122
    Abstract: A high-speed, high pin-out chip carrier package (10) for interconnecting at least one LSI or VLSI chip to a circuit pack is disclosed. The package includes a ground plane (19), a power plane (20), and at least one signal layer (15, 16, 17, 18) containing plural conductors therethrough. Layers (85) of dielectric material separate adjacent conductive layers, (15, 16, 17, 18, 19, 20). By controlling, in design, the width of each signal conductor and its distance to the nearest ground (19) or power plane (20), the package is impedance-matched to the circuit pack. Plural plated-through holes (21) are disposed through the package for electrically interconnecting the signal conductors, the ground plane (19), and the power plane (20) to the circuit pack, and are arranged in a pattern to reduce inductive noise.
    Type: Grant
    Filed: December 29, 1982
    Date of Patent: February 5, 1985
    Assignee: AT&T Bell Laboratories
    Inventor: Attilio J. Rainal
  • Hybrid integrated circuit component and printed circuit board mounting said component
    Patent number: 4495546
    Abstract: A hybrid integrated circuit component for insertion in a slit of a mother printed circuit board, and a method of mounting the hybrid integrated circuit component. The circuit component includes a flexible circuit board composed of a flexible insulated substrate, a circuit conductor formed on one side of the substrate, and a pair of conductor layers formed along opposite sides of the substrate to serve as external connection terminals. Circuit elements are mounted on the substrate and electrically connected to the circuit conductor.
    Type: Grant
    Filed: May 13, 1982
    Date of Patent: January 22, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsuneshi Nakamura, Tatsuro Kikuchi
  • Spacer for wiring boards and assembled structure thereof
    Patent number: 4495548
    Abstract: A spacer having an upper substrate at the center of which a coupling hole is formed, a lower substrate which is provided opposite to the upper substrate, and a plurality of support members bridging between the upper and the lower substrates so as to retain a space therebetween in which the mechanical strength against the loads applied in the horizontal direction as well as in the direction of twisting is extremely large, thus enabling the spacer according to the present invention to resist failure even if these large loads are applied thereto unlike the prior art spacers and thus obtaining a secured snap-fitting as well as thus making possibility of the spacer coming off from the wiring board difficult.
    Type: Grant
    Filed: November 12, 1982
    Date of Patent: January 22, 1985
    Assignee: Kitagawa Industries Co., Ltd.
    Inventor: Kazuhiro Matsui
  • Substrate wiring patterns for connecting to integrated-circuit chips
    Patent number: 4495377
    Abstract: An IC chip connects to a substrate by a pattern of pads arranged in single lines along the radial edges of segments of a polygon underlying the chip-linear conductors from the pads cross the outer edge of the segments in parallel groups. Wider power conductors can also be placed in the pattern.
    Type: Grant
    Filed: December 30, 1982
    Date of Patent: January 22, 1985
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Johnson, John M. Ryba
  • Heat-removing circuit boards
    Patent number: 4495378
    Abstract: The invention relates to circuit boards consisting of a flat core plate, 1 to 5 mm thick, of metallic material, graphite or electrically conductive carbon with a coating, 10 to 80 .mu.m thick, of electroplated aluminum eloxal and, optionally, an intermediate layer of copper or silver, 0.1 to 2 .mu.m thick. On the electroplated Al eloxal layer, a conductor run structure generated by an additive or subtractive technique may be present. The highly heat-conducting and mechanically strong circuit boards find application in electronics.
    Type: Grant
    Filed: August 22, 1983
    Date of Patent: January 22, 1985
    Assignee: Siemens Aktiengesellschaft
    Inventors: Richard Dotzer, Ernst-Friedrich Lechner
  • Connecting a cable to a P.C. board
    Patent number: 4494308
    Abstract: The individual conductors of a cable are connected to a P.C. board under utilization of an auxiliary member having a plate in which are inserted solder pins. The conductors of the cable are connected to one side of the pins, an insulated body is molded around that connection including the conductor ends and the end of the cable; the pins project in a particular pattern from the auxiliary member and are inserted in a matching pattern of solder sleeves in the P.C. board and the pins are soldered to the sleeves. The auxiliary member is separately bolted to the P.C. board.
    Type: Grant
    Filed: June 9, 1982
    Date of Patent: January 22, 1985
    Assignee: Kabelmetal Electro GmbH
    Inventor: Friedrich Schauer