Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract: In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.

Abstract: Structured glass articles include a glass substrate including a glass cladding layer fused to a glass core layer, a cavity formed in the glass substrate, and a shielding layer disposed within the cavity. In some embodiments, a passivation layer is disposed within the cavity such that the shielding layer is between the passivation layer and the glass substrate. A method for forming a glass fan-out includes depositing a shielding layer within a cavity in a glass substrate. The glass substrate includes a glass cladding layer fused to a glass core layer. A silicon chip may be deposited within the cavity. In some embodiments, the method also includes depositing a passivation layer within the cavity such that the shielding layer is between the passivation layer and the glass substrate.

Abstract: A method of manufacturing a semiconductor device is disclosed herein. The method includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: A power electronic component including a surface adapted to be attached to a heatsink, the surface forming a bottom surface of the power electronic component, one or more power electronic semiconductor chips mounted on a substrate above the bottom surface, and a housing enclosing the one or more power electronic semiconductor chips. The power electronic component includes a thermal insulator disposed above the one or more power electronic semiconductor chips, such that the bottom surface and the thermal insulator are on the opposite sides of the one or more power electronic semiconductor chips.

Abstract: A method of manufacturing a semiconductor structure includes the following operations. A buffer layer is formed over a substrate. A first top hard mask is formed on the buffer layer, in which the first top hard mask has a first trench to expose a first portion of the buffer layer. A spacer layer is formed to cover a sidewall of the first trench and an upper surface of the first top hard mask and the first portion of the buffer layer to form a second trench over the first portion. The top portion and the bottom portion are etched to form a thinned top portion and a thinned bottom portion. A second top hard mask is formed in the second trench. The thinned top portion and the vertical portion of the spacer layer are removed.

Abstract: An image sensor includes a substrate material, an array of the color filters, an array of waveguides and spacers. The substrate material includes a plurality of photodiodes disposed therein. The array of color filters are disposed over the substrate material. The array of waveguides are disposed over the substrate material. The buffer layer is disposed between the substrate material and the arrays of color filters and waveguides. The spacers are disposed between the color filters in the array of color filters. The spacers are disposed between the waveguides in the array of waveguides. Incident light is adapted to be confined between the spacers. The incident light is adapted to be directed through one of the waveguides and through one of the color filters prior to being directed through the buffer layer into one of the photodiodes in the substrate material.

Abstract: An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

Abstract: Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module).

Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

Abstract: A semiconductor structure that includes a semiconductor fin disposed over a substrate, S/D features disposed over the semiconductor fin, and a metal gate stack interposed between the S/D features. The metal gate stack includes a gate dielectric layer disposed over the semiconductor fin, a capping layer disposed over the gate dielectric layer, and a gate electrode disposed over the capping layer, where the gate dielectric layer includes hafnium oxide with hafnium atoms and oxygen atoms arranged in a Pca21 space group.

Abstract: Multiple theoretical reflectances determined by simulation for a silicon substrate with thin films of multiple types and thicknesses formed thereon are registered in association with the types and the thicknesses in a database. A carrier storing semiconductor wafers in a lot is transported into a heat treatment apparatus. A reflectance of a semiconductor wafer is measured by applying light to a surface of the semiconductor wafer. The theoretical reflectance of the semiconductor wafer is calculated from the measured reflectance thereof. A theoretical reflectance closely resembling the theoretical reflectance of the semiconductor wafer is extracted from among the multiple theoretical reflectances registered in the database, whereby the type and thickness of the thin film formed on the surface of the semiconductor wafer are specified. Treatment conditions for the semiconductor wafer are determined based on the specified type and thickness of the thin film.

Abstract: A method for forming a semiconductor device involves selecting a substrate on which a wurtzite III-nitride alloy layer will be formed, and a piezoelectric polarization and an effective piezoelectric coefficient for the wurtzite III-nitride alloy layer. It is determined whether there is a wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient. It is also determined whether there is a thickness for a layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization based on the selected substrate and the selected effective piezoelectric coefficient.

Abstract: The present invention discloses a MEMS device and electronic apparatus. The MEMS device comprises: a micro-LED; and a movable member, wherein the micro-LED is mounted on the movable member and is configured for moving with the movable member. According to an embodiment of this invention, the signal detection of a MEMS device can be simplified and/or the contents of signals produced by the MEMS device can be enriched.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.

Abstract: A method of forming a semiconductor structure is provided. The method includes etching a trench in a template layer over a substrate, forming a seed structure over a bottom surface of the trench, forming a dielectric cap over the seed structure, and growing a single crystal semiconductor structure within the trench using a vapor liquid solid epitaxy growth process. The single crystal semiconductor structure is grown from a liquid-solid interface between the seed structure and the bottom surface of the trench.

Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Abstract: A packaged electronic component comprising: an electronic component housed within a package comprising a front part of a package comprising an inner section with a front cavity therein opposite the electronic component defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads adapted to couple the package in a flip chip configuration to a circuit board.