Abstract: A method for manufacturing a semiconductor device includes: forming a first film on a substrate; forming a second film containing at least carbon on the first film; forming a hole in the second film; and forming a recess, which communicates with the hole, in the first film by etching using the second film as a mask. In this method, the second film includes a first layer formed on the first film, and a second layer formed on the first layer. The first layer having a higher oxygen concentration than the second layer.

Abstract: In a first aspect, the present invention relates to a nanopore field-effect transistor sensor (100), comprising: i) a source region (310) and a drain region (320), defining a source-drain axis; ii) a channel region (330) between the source region (310) and the drain region (320); iii) a nanopore (400), defined as an opening in the channel region (330) which completely crosses through the channel region (330), oriented at an angle to the source-drain axis, having a first orifice (410) and a second orifice (420), and being adapted for creating a non-linear potential profile between the first (410) and second (420) orifice.

Abstract: ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.

Abstract: The present invention relates to a substrate supporting device and a substrate processing apparatus. The substrate supporting device, the substrate supporting device of the substrate processing apparatus, may include: a disk; and a plurality of substrate supporting parts disposed radially from a center of the disk, a substrate being supported by each of the plurality of substrate supporting parts. An upper surface of each of the plurality of substrate supporting parts may protrude more upward than an upper surface of the disk.

Abstract: In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.

Abstract: An intermediate structure for forming a semiconductor device and method of making is provided. The intermediate device includes (i) a substrate comprising a Ga-based layer, and (ii) optionally, a metal layer on the substrate; wherein at least one of the Ga-based layer and, if present, the metal layer comprises at least a surface region having an isoelectric point of less than 7, usually at most 6.

Abstract: A wafer polishing method includes moving a polishing pad to a standby position where a gap is defined between the upper surface of a wafer held on a holding unit and the lower surface of the polishing pad, lowering the polishing pad from the standby position by a preset distance at a preset speed, determining whether or not a load measured by a load sensor is greater than or equal to a preset threshold value in a rest condition of the polishing pad after lowering the polishing pad, repeatedly the lowering the polishing pad until it is determined that the load measured by the load sensor is greater than or equal to the threshold value, and polishing the wafer in the condition where a load falling in a predetermined load range including the threshold value.

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.

Abstract: A method for manufacturing a semiconductor device (10) includes, in the following order: forming a first insulating film (14) on a semiconductor substrate (12); forming, on the first insulating film (14), wiring in which at least the uppermost layer is made of Au (16); implanting ions, which do not impair insulating properties even when implanted into the insulating film (14), into the upper surface of the wiring (16) and a region not covered with the wiring (16) on the upper surface of the first insulating film (14); and forming a second insulating film (18) that covers the wiring (16).

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

Abstract: Methods of conformally doping three dimensional structures are discussed. Some embodiments utilize conformal silicon films deposited on the structures. The silicon films are doped after deposition to comprise halogen atoms. The structures are then annealed to dope the structures with halogen atoms from the doped silicon films.

Abstract: A method for fabricating a semiconductor device includes providing a to-be-etched layer, including alternately arranged first regions and second regions along a first direction. Each second region includes a trench region. The method includes forming a first mask layer on the to-be-etched layer; forming a doped separation layer in the first mask layer on the second region of the to-be-etched layer to divide the first mask layer along a second direction perpendicular to the first direction; forming a first trench in the first mask layer on the first region; forming a separation filling layer to divide the first trench along the second direction; implanting doping ions into the first mask layer outside of the trench region; and removing the first mask layer formed in the trench region on both sides of the doped separation layer to form a second trench that is divided into portions along the second direction.

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Abstract: In a communication system, a communication terminal device transmits and receives RF signals frequently. Subsequent to an antenna of the communication terminal device, the communication terminal device includes a radio frequency switch (also referred to as transmit/receive (T/R) switch) that switches between two states at a high frequency, where one state is for receiving RF signal and other state for transmitting RF signal. In the exemplary embodiments of the disclosure, a complementary metal-oxide-semiconductor (CMOS) switch is provided, where the CMOS switch is deigned to have a high reliability by coupling a body of a transistor of the CMOS switch to a bias voltage through a switch, where the insertion loss and isolation are improved for the operation of the CMOS switch.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

Abstract: A method for locally annealing and crystallizing a thin film by directing ultrashort optical pulses from an ultrafast laser into the film. The ultrashort pulses can selectively produce an annealed pattern and/or activate dopants on the surface or within the film.

Abstract: An organic light-emitting diode includes: a first electrode, a light-emitting stack thereon including: a hole transport layer (HTL), a blue light-emitting layer including: a blue host material (BHM), and a blue fluorescent dopant (BFD) material, and an electron transport layer (ETL), and a second electrode on the light-emitting stack, wherein BFD LUMO>BHM, BFD HOMO>BHM, BFD singlet energy<BHM, HTL HOMO>BHM and BFD, HTL HOMO?BFD HOMO?0.1 eV, the HTL material LUMO>the BHM, HTL LUMO?BHM LUMO?0.5 eV, HTL LUMO>BFD, ETL LUMO>BHM and BFD, a difference in LUMO between the ETL material and the BFD material?0.1 eV, and the HTL material, the ETL material, and the BHM have the following triplet energy relationships: T1,BH<T1,HTL and T1,BH<T1,ETL, 2.8<T1,HTL<3.0, and 2.6<T1,ETL<2.8.

Abstract: A light-emitting device and a display including the same can improve the process stability during the process of disposing the light-emitting device. A light-emitting device includes the n-type semiconductor layer and the p-type semiconductor layer, and a structure is disposed so as to minimize electrical short between electrodes even if the light-emitting device is misaligned. The structure may have at least one side surface in an inverted taper shape and may be disposed between electrodes to minimize a short-circuit therebetween during the process of connecting the electrodes.

Abstract: The first object of the invention is directed to field-effect gate transistor comprising (a) a substrate, (b) a source terminal, (c) a drain terminal, and (d) a channel between the source terminal and the drain terminal, the channel being a layer of CuxCryO2 in which the y/x ratio is superior to 1. The field-effect gate transistor is remarkable in that the channel of CuxCryO2 presents a gradient of holes concentration. The second object of the invention is directed to a method for laser annealing a field-effect gate transistor in accordance with the first object of the invention.

Abstract: The present disclosure provides a semiconductor device with an air gap for reducing capacitive coupling in a pattern-dense region and a method for preparing the semiconductor device. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.