Patents Examined by Reginald Bragdon
  • Patent number: 9798488
    Abstract: In one embodiment, a method includes moving data from an original, unmoved stride from an original array to target stripes of a target stride in a distributed array in response to a determination that all target stripes of the target stride are in a blank state indicating no data is stored therein, delaying movement of the data from the original stride to the target stripes of the target stride in response to a determination that any of the target stripes of the target stride are in an old state indicating unmoved data is stored therein, and moving the data from the original stride to the target stripes of the target stride after delaying and in response to a determination that all the target stripes of the target stride that were in the old state have switched to the blank state.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chiahong Chen, Bo Cheng, Xue Dong Gao, David R. Kahler, Hai Bo Qian
  • Patent number: 9798661
    Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 24, 2017
    Assignee: HITACHI, LTD.
    Inventors: Yoshifumi Mimata, Yuko Matsui, Shintaro Kudo
  • Patent number: 9798498
    Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Jin Cho, Seong Nam Kwon, Hyun Seok Kim, Jae Geun Park, Seong Jun Ahn, Mi Hyang Lee
  • Patent number: 9798673
    Abstract: Techniques are disclosed relating to storing translations in memory that are usable to access data on a recording medium. In one embodiment, a request is sent for a memory allocation within a non-pageable portion of a memory in a computer system. Responsive to the request, allocated memory is received. Translations usable to map logical addresses to physical addresses within a storage device are stored within the allocated memory. In some embodiments, the translations are usable to access an area within the storage device used to store pages evicted from the memory. In one embodiment, a size of the memory allocation is determined based on a size of the area. In another embodiment, a size of the memory allocation is determined based on a size of a partition including the area. In some embodiments, the storage device is a solid-state storage array.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 24, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: James G. Peterson, Igor Sharovar, David Atkisson
  • Patent number: 9798478
    Abstract: An operating method of a storage device and a nonvolatile memory device determine whether a nonvolatile memory device performs a program operation on at least one of a plurality of pages. Either a program time stamp table, managed with program elapsed times of the plurality of pages, or an update count of the program time stamp table is updated, based on the determination result.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Hwan Choi, Byungjune Song
  • Patent number: 9792067
    Abstract: A device may comprise a plurality of non-volatile memory devices configured to store a plurality of physical pages and a controller coupled thereto, configured to program and read data to and from the plurality of non-volatile memory devices. The data may be stored in a plurality of logical pages (L-Pages) of non-zero length at starting addresses within the plurality of physical pages. The controller may be configured to execute first and second commands to indicate that first and second physical locations within the plurality of non-volatile memory devices no longer contain valid data and are now free space. This may be done by carrying out first and second virtual write operations of first and second L-Pages of a predetermined length at first and second unique addresses within a virtual address range that does not correspond to any of the physical pages, and accounting for an amount of free space gained as a result of executing the commands.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 17, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: Andrew J. Tomlin
  • Patent number: 9785562
    Abstract: Embodiments of the present invention provide methods, computer systems, and computer program products for adjusting allocation of a storage device. In one embodiment, a first part of the storage device is allocated to tiering storage, and a second part of the storage device is allocated to cache storage. Operating statuses of the first part and second part are collected. A performance measure of the first part is obtained based on the operating status of the first part, and a performance measure of the second part is obtained based on the operating status of the second part. Allocation of a capacity of the storage devices is adjusted between the first part and the second part based on the performance measures of the first part and the second part.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yang Liu, Yi Yang, Jun Wei Zhang, Xin Zhang
  • Patent number: 9785569
    Abstract: A method includes receiving a request to access a desired block of memory. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address comprising a most significant portion and a byte index. Locating an entry, in a buffer, the entry including the ESID of the effective address. Based on the entry including a radix page table pointer (RPTP), performing, using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Michael K. Gschwind
  • Patent number: 9785352
    Abstract: An application located in one or more first memory regions is executed. The application has a separate modified portion, which is located in one or more second memory regions. A request is obtained to access one of a first memory region or a second memory region, the request including an address of a first type. Based on obtaining the request, the address is translated to another address. The other address is of a second type and indicates the first memory region or the second memory region. The translating is based on an attribute associated with the address, in which the attribute is used to select information from a plurality of information concurrently available for selection. The plurality of information provide multiple addresses of the second type, one of which is the other address. The other address is used to access the first memory region or the second memory region.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9785559
    Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
  • Patent number: 9772782
    Abstract: The disclosed systems include features to mitigate a risk of data corruption attributable to unexpected power loss events. In particular, the disclosed system identifies and retrieves complement data associated with each received write command and stores the complement data in a non-volatile cache while the complement data is overwritten via execution of the write command.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: September 26, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Andrew Kowles, Timothy Feldman
  • Patent number: 9760492
    Abstract: A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a programmable hash function upon at least a portion of the memory address to generate a hashing address; and determining an index of the cache based at least partly on the hashing address.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: September 12, 2017
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Hsilin Huang, Cheng-Ying Ko, Hsin-Hao Chung, Chao-Chin Chen
  • Patent number: 9760481
    Abstract: A data storage device includes a memory that has a three-dimensional (3D) memory configuration, a controller, and a plurality of memory ports. The controller is configured to read mapping data from the memory. The mapping data maps the plurality of memory ports to the plurality of storage elements. The controller is further configured to, in response to receiving a command associated with a logical address, determine a physical address of the memory corresponding to the logical address, the physical address corresponding to a group of storage elements of the plurality of storage elements. The controller is further configured to select a memory port of the plurality of memory ports, where the memory port is mapped to the group of storage elements. The controller is further configured to access the group of storage elements via the memory port to perform first command.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 12, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Manuel Antonio D'Abreu
  • Patent number: 9760484
    Abstract: Embodiments of the present disclosure provide a data processing method and an electronic device. The method is applied in an electronic device, the electronic device being configured with a CPU and a UEFI BIOS; the CPU comprising at least two executing cores each capable of executing one thread; the method comprising: obtaining a first instruction for backup/recovery of designated data when the UEFI BIOS is started to run; invoking a second executing core of the CPU based on the first instruction; and executing the backup/recovery of the designated data by the UEFI BIOS and the second executing core, wherein the UEFI BIOS is run by a first executing core of the CPU.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: September 12, 2017
    Assignees: Beijing Lenovo Software Ltd., Lenovo (Beijing) Limited
    Inventor: Hongjiang Bi
  • Patent number: 9753860
    Abstract: Embodiments relate to managing page table entries in a processing system. A first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses is identified. The page table includes a second page table entry contiguous with the second page table entry. It is determined whether the first PTE may be joined with the second PTE based on the respective pages of main storage being contiguous. A marker is set in the page table for indicating that the main storage pages identified by the first PTE and second PTEs are contiguous.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Michael K. Gschwind
  • Patent number: 9753644
    Abstract: A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: September 5, 2017
    Assignee: Apple Inc.
    Inventors: Avraham Meir, Oren Golov
  • Patent number: 9747169
    Abstract: A data storage system can scan one or more information stores of primary storage and analyze the metadata of files stored in the one or more information stores of primary storage to identify multiple, possibly relevant, secondary copy operations that can be performed on the files. The storage system can also identify primary storage usage information of each file during the scan and use that information to generate reports regarding the usage of the primary storage.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: August 29, 2017
    Assignee: Commvault Systems, Inc.
    Inventors: Rajiv Kottomtharayil, Paramasivam Kumarasamy
  • Patent number: 9747216
    Abstract: A computer processor including a first memory structure that operates over multiple cycles to temporarily store operands referenced by at least one instruction. A plurality of functional units performs operations that produce and access operands stored in the first memory structure. A second memory structure is provided, separate from the first memory structure. The second memory structure is configured as a dedicated memory for storage of operands copied from the first memory structure. The second memory structure is organized with a byte-addressable memory space and each operand stored in the second memory structure is accessed by a given byte address into the byte-addressable memory space.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 29, 2017
    Assignee: Mill Computing, Inc.
    Inventors: Roger Rawson Godard, Arthur David Kahlich, Sebastien Paul Maurice Mirolo, David Arthur Yost
  • Patent number: 9747213
    Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 29, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
  • Patent number: 9740642
    Abstract: Methods and electronic devices for adjusting an operating frequency of a memory are disclosed. The method includes: transmitting to the memory a first command that instructs the memory to hold the data information in the memory; transmitting to the memory controller a second command that adjusts the first frequency of the memory controller to a second frequency; and transmitting to the memory a third command that instructs the memory to exchange the data information according to the second frequency of the memory controller. According to the disclosure, it is possible to dynamically adjust the frequency of the memory during operation, avoiding the need of the user to turn off and then turn on the electronic device to adjust the frequency of the memory.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: August 22, 2017
    Assignees: LENOVO (BEIJING) LIMITED, BEIJING LENOVO SOFTWARE LTD.
    Inventors: Jingang Peng, Xiaogang Wang, Xiaoyi Feng