Patents Examined by Richard T. Elms
  • Patent number: 7301805
    Abstract: The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can hold. In one embodiment, the present invention allows overlapped programming of upper and lower data pages, where once the memory begins programming the lower logical data page, if data is received for the upper page assigned to the same physical page, programming is interrupted and recommenced with the concurrent programming of both the upper and the loser pages. In a complimentary embodiment, when a page contains multiple sectors of data, programming of the physical page can begin when one or more, but less than all, of the sectors forming the corresponding logical page have been received, stopped and restarted to include additional sectors of the page.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: November 27, 2007
    Assignee: SanDisk Corporation
    Inventors: Sergey Anatolievich Gorobets, Yan Li
  • Patent number: 7301822
    Abstract: A programmable device having a multi-boot capability is described. The programmable device may initially load first configuration data for configuring programmable resources of the device. Thereafter, a multi-boot operation may be triggered, causing the device to reconfigure and load second configuration data. Prior to loading the second configuration data, the device may store status information. In some cases, further multi-boot operations may be triggered for loading other configuration data.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: November 27, 2007
    Assignee: Xilinx, Inc.
    Inventors: James A. Walstrum, Jr., Wayne E. Wennekamp, Eric E. Edwards
  • Patent number: 7301794
    Abstract: A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has current injectors ready to operate if program line voltages are appropriate to cause charge storage in a memory cell, while a cell in an adjacent row be erased by charge being driven from a memory transistor. A series of conductive plates are arranged over the word line, with each plate having a pair of oppositely extending tangs, one causing programming of a cell in a first row and another causing erasing of a cell in another row.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: November 27, 2007
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek
  • Patent number: 7301811
    Abstract: A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in a first polysilicon layer, and a tunnel window formed in a tunnel oxide area, wherein the tunnel oxide area is covered by at least a portion of the floating gate. The control gate may control charge on the floating gate, and may be formed in a second polysilicon layer, wherein the second polysilicon layer is above the first polysilicon layer.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 27, 2007
    Assignee: Xilinx, Inc.
    Inventor: Sunhom Paak
  • Patent number: 7298656
    Abstract: An evaluation circuit includes a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured to convert the first reference voltage into a second delay, and a first latching circuit configured to determine a relationship between the first delay and the second delay.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: November 20, 2007
    Assignee: Infineon Technologies AG
    Inventor: Alessandro Minzoni
  • Patent number: 7298640
    Abstract: A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: November 20, 2007
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Zheng Chen, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 7298643
    Abstract: A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment vector being associated with each layer, the resulting magnetic moment vector, equal to the sum of the layer magnetic moment vectors, having an amplitude smaller than at least 40% of the amplitude of the layer magnetic moment vector of maximum amplitude. The anisotropy field and/or the demagnetizing field tensor is not identical for the at least two ferromagnetic layers, whereby the angular deviations of the layer magnetic moment vectors are different at the time of the application of an external magnetic field, which enables at least two methods for directly writing into the memory element, as well as its initialization.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: November 20, 2007
    Assignees: STMicroelectronics SA, Centre National de la Recherche Scientifique, Universite de Paris SUD (Paris XI)
    Inventors: Joo-Von Kim, Thibaut Devolder, Claude Chappert, Cedric Maufront, Richard Fournel
  • Patent number: 7297615
    Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
  • Patent number: 7295458
    Abstract: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: November 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, William V. Huott, Donald W. Plass
  • Patent number: 7295487
    Abstract: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: November 13, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, Prashant U. Kenkare, Jeremiah T. C. Palmer
  • Patent number: 7295477
    Abstract: A semiconductor memory device comprises a wordline (40), a first bitline (21a), two second bitlines (22a, 22b), a first memory cell (100a) and a second memory cell (100b). The first memory cell (100a) is coupled to the wordline (40), one of the second bitlines (22a) and the first bitline (21a). The second memory cell (100b) is coupled to the wordline (40), the other second bitline (22b) and the first bitline (21a). Each memory cell (100a, 100b) stores a first bit (101) and a second bit (102). The semiconductor device further comprises a programming unit (2) coupled to the wordline (40) and the first and the second bitlines (21a, 22a, 22b).
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 13, 2007
    Assignee: Infineon Technologies Flash GmbH & Co. KG
    Inventors: Luca de Ambroggi, Thomas Kern
  • Patent number: 7295479
    Abstract: A method and an apparatus for managing bad blocks generated while a flash memory is being used. A method for managing a bad block in a flash memory includes (a) allocating a used area having a plurality of used blocks and a spare area having a plurality of spare blocks in the flash memory, and providing a block map page group including a plurality of block map pages in which mapping information to map a bad block generated in either of the used area or the spare block to a spare block, (b) having mapping information of the block map page reside among the block map page groups in the memory, and (c) mapping the bad block generated during a flash operation to an unused spare block found through the mapping information, updating the mapping information, and recording the updated mapping information on the block map page.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Song-ho Yoon, Jang-hwan Kim, Bum-soo Kim, Tae-sun Chung, Ji-hyun In
  • Patent number: 7295483
    Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: November 13, 2007
    Assignee: Fujitsu Limted
    Inventors: Naoharu Shinozaki, Yasurou Matsuzaki
  • Patent number: 7295478
    Abstract: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: November 13, 2007
    Assignee: SanDisk Corporation
    Inventors: Jun Wan, Jeffrey Lutze, Masaaki Higashitani, Gerrit Jan Hemink, Ken Oowada, Jian Chen, Geoffrey S. Gongwer
  • Patent number: 7295485
    Abstract: The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: November 13, 2007
    Assignee: Atmel Corporation
    Inventors: Stanley Hong, Jami Wang, Alan Chen
  • Patent number: 7292473
    Abstract: A non-volatile memory (NVM) that can be optimized for data retention or endurance is divided into portions that are optimized for one or the other or potentially some other storage characteristic. For the portion allotted for data retention, the memory cells are erased to a relatively greater extent. For the portion allotted for high endurance, the memory cells are erased to a relatively lesser extent. This is conveniently achieved by simply raising the level of the current reference that is used to determine if a cell has been sufficiently erased for the high data retention cells. The higher endurance cells thus will typically receive fewer erase pulses than the memory cells for high data retention. The reduced erasing requirement for the high endurance cells results in overall faster erasing and less stress on the high endurance cells as well as on the circuitry that generates the high erase voltages.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: November 6, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Martin L. Niset, Andrew W. Hardell
  • Patent number: 7292479
    Abstract: A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier. Binary data signals read out from the memory cell are amplified and evaluated. The binary data signals can also be written back to the corresponding memory cell. Furthermore, an output unit for outputting the amplified and evaluated binary data signals and a coupling device between the memory cell array and the sense amplifier are provided. The coupling device has a preamplifier unit for preamplifying the data signals read out and a bridging unit for bridging the preamplifier unit in order to provide a writing back of the binary data signals to the memory cell of the memory cell array.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: November 6, 2007
    Assignee: Infineon Technolgoies AG
    Inventors: Sven Boldt, Erwin Thalmann
  • Patent number: 7292474
    Abstract: A semiconductor integrated circuit device has a memory cell array including a plurality of pages and a page buffer. Each of the plurality of pages includes a user region and a page flag region in which page flag data indicative of a current state of a corresponding page is written. The page buffer includes a user page buffer section which temporarily holds the user data and a page flag page buffer section which temporarily holds the page flag data. The page flag data is recorded in the form of two levels in the non-volatile semiconductor memory cell arranged in the page flag region. The user data is recorded in the form of multilevel in the non-volatile semiconductor memory cell arranged in the user region.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: November 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naohisa Iino, Fumitaka Arai
  • Patent number: 7289344
    Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of a neighbor memory cell if the neighbor memory cell was programmed subsequent to the given memory cell. Techniques for determining whether the neighbor memory cell was programmed before or after the given memory cell are disclosed.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: October 30, 2007
    Assignee: Sandisk Corporation
    Inventor: Jian Chen
  • Patent number: 7289385
    Abstract: Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank selection signal control circuit includes a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect memory banks to a global data input/output line according to a predetermined sequence. For memory bank selected prior to a last selected memory bank in the predetermined sequence, the bank switch control unit outputs memory bank selection control signals that are enabled for a first time period P1, and for the last selected memory bank, the bank switch control unit outputs a memory bank selection control signal that is enabled for a second time period P2, wherein P2 is greater than P1.
    Type: Grant
    Filed: November 12, 2005
    Date of Patent: October 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-Seok Kwak