Patents Examined by Richard T. Elms
  • Patent number: 7349251
    Abstract: A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properties of the memory circuit arrangement.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: March 25, 2008
    Assignee: Infineon Technologies AG
    Inventor: Georg Tempel
  • Patent number: 7345943
    Abstract: An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes an output voltage based on a state of the eFUSE, and the differential amplifier changes the output voltage into a digital output with no clocking capabilities.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: March 18, 2008
    Assignee: International Business Machines Corporation
    Inventor: Larry Wissel
  • Patent number: 7345921
    Abstract: Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: March 18, 2008
    Assignee: Atmel Corporation
    Inventors: Stefano Surico, Simone Bartoli, Fabio Tassan Caser, Monica Marziani
  • Patent number: 7345947
    Abstract: Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Jeffrey L. Miller, Mahadevamurty Nemani, James W. Conary
  • Patent number: 7345898
    Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: March 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-dong Park, Jo-won Lee, Chung-woo Kim, Eun-hong Lee, Sun-ae Seo, Woo-joo Kim, Hee-soon Chae, Soo-doo Chae, I-hun Song
  • Patent number: 7342841
    Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Sandeep K. Jain, Animesh Mishra, John B. Halbert
  • Patent number: 7342846
    Abstract: Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: March 11, 2008
    Assignee: Lattice Semiconductor Corporation
    Inventors: Louis De La Cruz, Allen R. White, Hemanshu T. Vernenker
  • Patent number: 7342817
    Abstract: A system for writing data using an electron beam to change the structure of a small section of a storage medium and includes at least one focused electron beam source. The duration of a write cycle of the focused electron beam source is controlled at least in part on an estimated or measured amount of charge transmitted by the focused electron beam source to the storage medium during the write cycle.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: March 11, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Alexander Govyadinov, Curt Van Lydegraf, David Schut
  • Patent number: 7342835
    Abstract: A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read data from and write data to the selected wordline. A buffer of latches are coupled to the group of first sense amplifiers and have sufficient capacity to hold data corresponding to the selected wordline of memory cells.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: March 11, 2008
    Assignee: Winbond Electronics Corp.
    Inventors: Ying Te Tu, Yu Chang Lin
  • Patent number: 7339844
    Abstract: A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure counts are preloaded with the respective values of redundant rows and columns available for repairing the device. When failures in memory cells of the device are encountered, either during test, or during scan of an earlier generated error image, the row and column failure counts associated with the rows and columns containing the memory cell failures are decremented. At the end of a test, the value of the failure counts indicates whether the corresponding row or column contain any failures at all, whether the corresponding row or column is designated as a “must-repair” row or column, and otherwise how many errors the corresponding row or column contain.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 4, 2008
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Alan S. Krech, Jr., Stephen D. Jordan, John M. Freeseman
  • Patent number: 7339851
    Abstract: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: March 4, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Chern Lee
  • Patent number: 7339840
    Abstract: A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: March 4, 2008
    Assignee: Infineon Technologies AG
    Inventors: Paul Wallner, Ralf Schledz, Peter Gregorius, Hermann Ruckerbauer
  • Patent number: 7339810
    Abstract: A search engine system (100) can include a key multiplexer (104) and logic circuit (108). A key from a previous operation can be received by logic circuit (108) and altered to generate an idle key. In a non-search operation, the idle key can be applied to a CAM section to draw current as in a normal search operation. Logic circuit (108) can ensure that an idle key value is always different than a previously applied key value.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: March 4, 2008
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Scott Smith
  • Patent number: 7336527
    Abstract: An electromechanical storage device includes an input element that facilitates the input of data, a series of data elements, and a terminating element that facilitates the reading out of data. The data elements each have at least two stable mechanical orientations, and these orientations can be utilized to store data. Data may be entered into the device by applying a transient electromagnetic pulse to the data elements. The device is constructed such that as a data bit is entered into the series of data elements, any data bits that have been previously entered into the series are shifted towards the terminating element.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventor: Gary Miles McClelland
  • Patent number: 7327629
    Abstract: An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and compare a sense current at the sense node relative to the reference current. The sensing circuit generates an output signal having a first logic level in response to the sense current being greater than the reference current and generates the output signal having a second logic level in response to the sense current being less than the reference current. The logic level of the output signal indicative of whether the antifuse is programmed or un-programmed.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: February 5, 2008
    Assignee: Micron Technology, Inc
    Inventors: Dong Pan, Abhay Dixit
  • Patent number: 7327628
    Abstract: An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and compare a sense current at the sense node relative to the reference current. The sensing circuit generates an output signal having a first logic level in response to the sense current being greater than the reference current and generates the output signal having a second logic level in response to the sense current being less than the reference current. The logic level of the output signal indicative of whether the antifuse is programmed or un-programmed.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: February 5, 2008
    Assignee: Micron Technology, Inc
    Inventors: Dong Pan, Abhay Dixit
  • Patent number: 7327598
    Abstract: An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical grouping of memory cells, configured to bias a subset of the set based on a memory address associated therewith. In another embodiment, a method includes receiving a memory address associated with the hierarchical grouping of memory cells and biasing a subset of the hierarchical grouping of memory cells based on the memory address.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: February 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Luan Dang, Hiep Van Tran
  • Patent number: 7324388
    Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Koji Kishi, Hideaki Kurata, Satoshi Noda, Yusuke Jono
  • Patent number: 7324379
    Abstract: A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 29, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicola Del Gatto, Massimiliano Mollichelli, Massimiliano Scotti, Marco Sforzin
  • Patent number: 7321523
    Abstract: A monitoring system capable of monitoring utilization of a processing device in a computer. The monitoring system includes a power supply voltage for supplying a core voltage to the processing device, and a comparator for comparing a voltage proportional to the core voltage to a reference voltage and producing a sense voltage. The resulting sense voltage is used to control a processing device management process, or alternatively may be used to control a variety of other processes including cooling fan operation.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: January 22, 2008
    Assignee: ASUSTeK Computer Inc.
    Inventor: Jia-Min Ke