Patents Examined by Richard T. Elms
  • Patent number: 7321524
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: January 22, 2008
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 7321514
    Abstract: The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which comprises in each case a first gate electrode and also a rear side electrode. The memory cell arrangement contains word lines and also rear side electrode lines which are arranged in each case alternately between adjacent cell columns. The invention provides for in each case the first gate electrodes of adjacent cell columns to be connected to the word line lying between the cell columns and in each case the rear side electrodes of adjacent cell columns to be connected to the rear side line lying between the cell columns. All the rear side lines are held at a constant potential, while for reading from a memory cell that word line is addressed to which the first gate electrode of the memory cell to be read is connected.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: January 22, 2008
    Assignee: Infineon Technologies AG
    Inventor: Ulrike Gruening-von Schwerin
  • Patent number: 7319627
    Abstract: A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirror circuit. A selection gate transistor and a detection transistor of the selected non-volatile memory cell are included as part of a load circuit connected to a drain electrode of the second mirror transistor. The detection transistor has a drain electrode linked to a source electrode of the selection gate transistor. An operating current of the selection gate transistor is smaller than an operating current of the detection transistor, and an electric current output from the second mirror transistor is determined by the operating current of the selection gate transistor. This arrangement enables determination of the stable operating current of the memory cell irrespective of the state of a floating gate of the detection transistor.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: January 15, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Kazuo Taguchi
  • Patent number: 7319608
    Abstract: A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Louis L. C. Hsu, Brian L. Ji, Chung Hon Lam, Hon-Sum Philip Wong
  • Patent number: 7319621
    Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a method according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: January 15, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Ben Ba
  • Patent number: 7317650
    Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: January 8, 2008
    Assignee: Fujitsu Limited
    Inventors: Naoharu Shinozaki, Yasurou Matsuzaki
  • Patent number: 7315467
    Abstract: The present invention relates to a magnetoresistive hybrid memory cell comprising a first stacked structure comprising a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein said first magnetic region being provided with a fixed first magnetic moment vector and said second magnetic region being provided with a free second magnetic moment vector which is free to be switched between the same and opposite directions with respect to said fixed first magnetic moment vector of said first magnetic region, a second stacked structure being at least partly arranged in a lateral relationship as to said first stacked structure and comprising a third magnetic region being provided with a fixed third magnetic moment vector and said second magnetic region; wherein said first and second structures being arranged in between at least two electrodes in electrical contact therewith.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: January 1, 2008
    Assignees: Infineon Technologies AG, Altis Semiconductor SNC, Centre National de la Recherche Scientifique (CNRS), Universite Paris-SUD
    Inventors: Jacques Miltat, Yoshinobu Nakatani
  • Patent number: 7312100
    Abstract: This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a method is provided that involves contacting a surface/electrode with a compound of formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: December 25, 2007
    Assignee: The North Carolina State University
    Inventors: David F. Bocian, Werner G. Kuhr, Jonathan S. Lindsey, Veena Misra
  • Patent number: 7313023
    Abstract: The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors turn on or off depending on the selected word line location in the array. Since bit line capacitance is mainly from the metal bit line to bit line coupling to their immediate neighbors, the bit line neighbors in the partitioned array are floating in some segments of the bit lines. The overall bit line capacitance is significantly reduced with a negligible increase in die size, resulting in reduced sensing times and enhanced read and write performance.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: December 25, 2007
    Assignee: SanDisk Corporation
    Inventors: Yan Li, Farookh Moogat
  • Patent number: 7310283
    Abstract: An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially delaying the internal clock to output a plurality of delayed clocks; a phase detecting block for detecting logic levels of the delayed clocks at a rising edge of the internal clock to output phase detecting signals; a sampling pulse generator for outputting a sampling signal generated at a predetermined point of the internal clock; a latching block for outputting a phase detection latch signal by sampling and latching the phase detection signal at a point of the sampling signal being inputted; and a frequency detection block for outputting the frequency detection signal by logically combining the phase detection latch signal.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: December 18, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hwang Hur, Jun-Gi Choi
  • Patent number: 7310255
    Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: December 18, 2007
    Assignee: SanDisk Corporation
    Inventor: Siu Lung Chan
  • Patent number: 7310282
    Abstract: A method and circuit for preventing the overprogramming of a memory cell. A fuse circuit is operable to be blown. A combinational logic circuit receives a signal from the fuse circuit, indicating whether or not the fuse has been blown, and controls the programming of the memory cell. The programming of the memory cell is prevented if the fuse circuit has been blown.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 18, 2007
    Assignee: Lexmark International, Inc.
    Inventors: John Glenn Edelen, Nicole Marie Rodriguez
  • Patent number: 7307905
    Abstract: Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: December 11, 2007
    Assignee: The Governing Council of the University of Toronto
    Inventors: Farid N. Najm, Navid Azizi, Andreas Moshovos
  • Patent number: 7307887
    Abstract: Temporary lock-out is provided while programming a group of non-volatile memory cells to more accurately program the memory cells. After successfully verifying that the threshold voltage of a memory cell has reached the level for its intended state, it is possible that the threshold voltage will subsequently decrease to below the verify level during additional iterations of the programming process needed to complete programming of other memory cells of the group. Memory cells are monitored (e.g., after each iteration) to determine if they fall below the verify level after previously verifying that the target threshold voltage has been reached. Cells that pass verification and then subsequently fail verification can be subjected to further programming. For example, the bit line voltage for the memory cell of interest may be set to a moderately high voltage to slow down or reduce the amount of programming accomplished by each subsequent programming pulse.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: December 11, 2007
    Assignee: SanDisk Corporation
    Inventor: Jian Chen
  • Patent number: 7304360
    Abstract: A super-paramagnetic cladding layer formed on from 1 to 3 sides of a conductive line in a magnetic device is disclosed. The cladding layer is made of “x” ML/SL stacks in which x is between 5 and 50, SL is an amorphous AlOx seed layer, and ML is a composite with a soft magnetic layer comprised of discontinuous particles less than 2 nm in size on the seed layer and a capping layer of Ru, Ta, or Cu on the soft magnetic layer. Fringing fields and hysteresis effects from continuous ferromagnetic cladding layers associated with switching the magnetic state of an adjacent MTJ are totally eliminated because of the super-paramagnetic character of the soft magnetic layer at room temperature. The soft magnetic layer has near zero magnetostriction, very high susceptibility, and may be made of Ni˜80Fe˜20, Ni˜30Fe˜70, Co˜90Fe˜10, or CoNiFe.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: December 4, 2007
    Assignee: MagIC Technologies, Inc.
    Inventors: Yimin Guo, Po-Kang Wang
  • Patent number: 7304896
    Abstract: A method for simultaneously programming a pre-established number of memory cells includes setting an initial number of memory cells to be simultaneously programmed equal to the pre-established number, and subdividing the initial number of memory cells to be programmed into subsets of memory cells. A program operation for simultaneously programming all the memory cells of each subset of memory cells is executed by forcing a current through all the memory cells of each subset of memory cells. The current has a program voltage associated therewith. The program voltage is compared to a threshold voltage during execution of the program operation. The method further includes stopping execution of the program operation if the threshold voltage is surpassed, reducing the initial number of memory cells to be simultaneously programmed, and restarting from the subdividing.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: December 4, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ignazio Martines, Michele La Placa
  • Patent number: 7304878
    Abstract: An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent power-up operations, intrusion is prevented.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: December 4, 2007
    Assignee: Atmel Corporation
    Inventors: Vincent Gosmain, Florent Garcia
  • Patent number: 7304890
    Abstract: A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: December 4, 2007
    Assignee: Atmel Corporation
    Inventors: Emil Lambrache, Duncan Curry, Richard F. Pang
  • Patent number: 7304887
    Abstract: A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device. The method of fabricating the memory device includes fabricating a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, fabricating a second layer of MRAM memory cells over the first layer of MRAM memory cells, and fabricating a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: December 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Frederick A. Perner
  • Patent number: 7301795
    Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: November 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John Y. Fong, Anand Seshadri, Sung-Wei Lin, Sudhir Kumar Madan, Jarrod Eliason