Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Abstract: Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings, arrays, and devices, include vertical Flash memory cells to form NAND architecture memory cell strings and memory arrays. These vertical memory cell NAND architecture strings allow for an improved high density memory devices or arrays that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and still allow for appropriate device sizing for operational considerations.

Abstract: A tunneling magneto-resistance element is arranged on an upper layer side of a digit line. The tunneling magneto-resistance element is electrically coupled to a source/drain region of an access transistor through a strap and a contact hole. A bit line is electrically coupled to the tunneling magneto-resistance element, and arranged on the upper layer side of the tunneling magneto-resistance element. A plurality of tunneling magneto-resistance elements share one access transistor, so that a non-volatile memory device achieving low area penalty and higher integration can be implemented.

Abstract: A method and system include providing a pinned layer, a free layer, and a spacer layer between the pinned and free layers. The spacer layer is nonmagnetic. The magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element. In one aspect, the method and system include providing a spin engineered layer adjacent to the free layer. The spin engineered layer is configured to more strongly scatter majority electrons than minority electrons. In another aspect, at least one of the pinned, free, and spacer layers is a spin engineered layer having an internal spin engineered layer configured to more strongly scatter majority electrons than minority electrons. In this aspect, the magnetic element may include another pinned layer and a barrier layer between the free and pinned layers.

Abstract: The present invention relates to an arrangement for increasing a relative change in resistance of a magnetoresistive memory cell (17) having in each case a memory layer (1) and a reference layer (3) on both sides of a tunnel barrier (2), the reference layer (3) being fashioned as a magnetically soft layer, and the magnetization thereof, which can be influenced by write operations, being oriented correctly again by a reference backup field or a reference magnetization current (11).

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract: The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.

Abstract: A submount for mounting an LED chip includes a substrate, a die attach pad configured to receive an LED chip on an upper surface of the substrate, a first meniscus control feature on the substrate surrounding the die attach pad and defining a first encapsulant region of the upper surface of the substrate, and a second meniscus control feature on the substrate surrounding the first encapsulant region and defining a second encapsulant region of the upper surface of the substrate. The first and second meniscus control features may be substantially coplanar with the die attach pad. A packaged LED includes a submount as described above and further includes an LED chip on the die attach pad, a first encapsulant on the substrate within the first encapsulant region, and a second encapsulant on the substrate within the second encapsulant region and covering the first encapsulant.

Abstract: A method for manufacturing semiconductor device employs an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film are formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film uses the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.

Abstract: A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

Abstract: A low-power memory device that uses hole-mediated ferromagnetism creates substantial advantages over conventional systems. Some of these advantages include reducing power consumption by several orders of magnitude and facilitating wireless monitoring of memory cells. In one implementation, an electronic device is described that includes a plurality of memory cells. Each of the memory cells has a material with first and second magnetic states. The material is in the first magnetic state when a contact associated with the material is at a first voltage, and the material is in the second magnetic state when the contact is at a second voltage. A conductor is positioned proximate to and extending around the plurality of memory cells. An inductive voltage across the conductor varies when at least one of the memory cells changes magnetic state. A detection device determines the magnetic state of the memory cells based on an inductive voltage measurement.

Abstract: An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range of input signal levels while improving the symmetry between rising and falling signal transitions of the output signal.

Abstract: A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing the selected word line with a selected word line voltage for performing the reading operation.

Abstract: A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selectively decouple the driving signal trace from said global bit trace.

Abstract: A memory tag is powered by and addressable via a radio frequency wireless link to read data from a memory. The memory tag is addressable by a reader. The memory holds data and interface configuration information relating to the operation of an interface device. This interface configuration information including at least one status item and an item type associated with the, or each, status item.

Abstract: A self refresh period signal generating device includes an internal temperature sensor; an extended mode register set for storing a first temperature code which corresponds to temperature measured by an external temperature sensor; a selection means for selecting one of the first temperature code included in the extended mode register set and a second temperature code which corresponds to temperature measured by the internal temperature sensor; and a self refresh period signal generating means for generating a temperature compensated self refresh period signal in response to an output signal from the selection means.

Abstract: Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.

Abstract: A magnetoresistive element includes a first ferromagnetic layer having a first magnetization, the first magnetization having a first pattern when the magnetoresistive element is half-selected during a first data write, a second pattern when the magnetoresistive element is selected during a second data write, and a third pattern of residual magnetization, the first pattern being different from the second and third pattern, a second ferromagnetic layer having a second magnetization, and a nonmagnetic layer arranged between the first ferromagnetic layer and the second ferromagnetic layer and having a tunnel conductance changing dependent on a relative angle between the first magnetization and the second magnetization.

Abstract: A semiconductor memory device disclosed herein includes: a first select gate line, a gate electrode of a first select transistor connected to the first select gate line; a second select gate line, a gate electrode of a second select transistor connected to the second select gate line; and word lines between the first select gate line and the second select gate line, gate electrodes of memory cells being respectively connected to the word lines, wherein when data in a memory cell connected to a first adjacent word line which is adjacent to the first select gate line is read, a voltage of the second select gate line is increased after a voltage of the first select gate line is increased, and when data in a memory cell connected to a second adjacent word line adjacent to the second select gate line is read, the voltage of the first select gate line is increased after the voltage of the second gate line is increased.

Abstract: A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation.