Patents Examined by Roberts P Culbert
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Patent number: 11295936Abstract: The substrate treating apparatus includes a processing module and an index module on which a cassette having the substrate received therein is placed and that includes an index robot that transfers the substrate between the cassette and the processing module. The processing module includes a process chamber and a transfer chamber. The process chamber includes a support unit. The support unit includes a support on which the substrate is placed and a ring member that surrounds the substrate placed on the support and that is provided so as to be detachable from the support. The apparatus further includes a carrier storage unit that stores a carrier that is mounted on a hand of the main transfer robot or the index robot and on which the ring member is placed when the ring member is transferred by the main transfer robot or the index robot.Type: GrantFiled: February 18, 2020Date of Patent: April 5, 2022Assignee: Semes Co., Ltd.Inventors: Dukhyun Son, Byung Kyu Kim
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Patent number: 11295948Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: GrantFiled: March 15, 2021Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Patent number: 11295960Abstract: A method of etching a silicon oxide film with high precision at high selectivity as compared with a silicon nitride film while establishing both of a higher etching rate of the silicon oxide film and a lower etching rate of the silicon nitride film is provided. An etching method according to the present invention is directed to a dry etching method for etching a film structure without using plasma in which an end of a film layer having a silicon oxide film vertically sandwiched between silicon nitride films and laminated and formed in advance on a wafer disposed in a processing chamber forms a side wall of a groove or a hole while a processing gas is supplied into the processing chamber, the method including the steps of: supplying a hydrogen fluoride gas; cooling the wafer to a low temperature of ?30° C. or lower, preferably, to ?30 to ?60° C.; and etching the silicon oxide film laterally from the end.Type: GrantFiled: March 9, 2021Date of Patent: April 5, 2022Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Takashi Hattori, Masaki Yamada, Michael Walker, Catherine King, Hiroto Otake
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Patent number: 11289325Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.Type: GrantFiled: February 19, 2021Date of Patent: March 29, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Michael Edley, Xinghua Sun, Yen-Tien Lu, Angelique Raley, Henan Zhang, Hiroyuki Suzuki, Shan Hu
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Patent number: 11289342Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.Type: GrantFiled: June 15, 2020Date of Patent: March 29, 2022Assignee: Applied Materials, Inc.Inventors: He Ren, Jong Mun Kim, Maximillian Clemons, Minrui Yu, Mehul Naik, Chentsau Ying
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Patent number: 11282711Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.Type: GrantFiled: July 31, 2020Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
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Patent number: 11282713Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes etching the first film with first gas including carbon and fluorine to form a concave portion in the first film and form a second film in the concave portion. The method further includes treating the second film by using the second film to second gas or second liquid, wherein the second film is treated without plasma.Type: GrantFiled: February 11, 2021Date of Patent: March 22, 2022Assignee: Kioxia CorporationInventor: Atsushi Takahashi
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Patent number: 11282714Abstract: The etching method of the present invention includes the step of supplying a first mixed gas containing a ?-diketone-containing etching gas and a nitrogen oxide gas to a target having, on a surface, both a first metal film containing cobalt, iron, or manganese and a second metal film containing copper, thereby selectively etching the first metal film over the second metal film, or the step of supplying a second mixed gas containing a ?-diketone-containing etching gas and oxygen gas to the target, thereby selectively etching the second metal film over the first metal film.Type: GrantFiled: May 31, 2017Date of Patent: March 22, 2022Assignees: CENTRAL GLASS COMPANY, LIMITED, TOKYO ELECTRON LIMITEDInventors: Akifumi Yao, Kunihiro Yamauchi, Tatsuo Miyazaki, Jun Lin, Susumu Yamauchi, Kazuaki Nishimura
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Patent number: 11274230Abstract: An aqueous alkaline chemical mechanical polishing composition includes a quaternary phosphonium compound having aromatic groups which enables enhanced reduction of defects on silicon oxide substrates and enables good silicon oxide removal rates during chemical mechanical polishing. The chemical mechanical polishing composition is stable.Type: GrantFiled: April 27, 2021Date of Patent: March 15, 2022Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventor: Yi Guo
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Patent number: 11267989Abstract: A polishing liquid used for chemical mechanical polishing includes colloidal silica, in which a zeta potential of the colloidal silica measured in a state where the colloidal silica is present in the polishing liquid is ?20 mV or less, an electrical conductivity is 200 ?S/cm or less, a pH is 2 to 6, and a transmittance is 70% to 99%.Type: GrantFiled: August 4, 2020Date of Patent: March 8, 2022Assignee: FUJIFILM CorporationInventor: Tetsuya Kamimura
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Patent number: 11267988Abstract: A polishing liquid is a polishing liquid used for chemical mechanical polishing, the polishing liquid including colloidal silica; and a buffering agent excluding phosphoric acid, in which the buffering agent is a compound having a pKa within a range of X±1 in a case where a pH of the polishing liquid is denoted by X, a zeta potential of the colloidal silica measured in a state where the colloidal silica is present in the polishing liquid is ?20 mV or less, an electrical conductivity is 200 ?S/cm or more, and a pH is 2 to 6.Type: GrantFiled: July 27, 2020Date of Patent: March 8, 2022Assignee: FUJIFILM CorporationInventor: Tetsuya Kamimura
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Patent number: 11251049Abstract: In an etching method, a target object temperature is maintained within a range from ?30° C. to 30° C. When a flow rate of an ith fluorocarbon gas in one or multiple fluorocarbon gases is referred to as J(i); a number of fluorine atoms and a number of carbon atoms in the corresponding gas are referred to as M(i) and N(i), respectively; a value calculated by summing J(i)×N(i)/M(i) of all values that i can be is referred to as Ua; a flow rate of a kth hydrogen-containing gas in one or multiple hydrogen-containing gases is referred to as J(k); a number of hydrogen atoms in the corresponding gas is referred to as H(k); and a value calculated by summing J(k)×H(k) of all values that k can be is referred to as Ub, Ua/Ub satisfies a condition of 0.04<Ua/Ub<0.22.Type: GrantFiled: April 6, 2020Date of Patent: February 15, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Taku Gohira, Masahiro Tadokoro
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Patent number: 11239093Abstract: The present invention provides a method for treating a substrate, which can remove transition metal-containing substances on a substrate with high efficiency while inhibiting cerium from remaining on the surface of the treated substrate. Furthermore, the present invention provides a method for manufacturing a semiconductor device including the method for treating a substrate, and a kit for treating a substrate that is applicable to the method for treating a substrate.Type: GrantFiled: July 27, 2020Date of Patent: February 1, 2022Assignee: FUJIFILM CorporationInventors: Tomonori Takahashi, Nobuaki Sugimura, Hiroyuki Seki
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Patent number: 11230769Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.Type: GrantFiled: May 22, 2020Date of Patent: January 25, 2022Assignee: ASM IP HOLDING B.V.Inventors: Tom E. Blomberg, Varun Sharma, Suvi P. Haukka, Marko J. Tuominen, Chiyu Zhu
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Patent number: 11230770Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.Type: GrantFiled: May 22, 2020Date of Patent: January 25, 2022Assignee: ASM IP HOLDING B.V.Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
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Patent number: 11217448Abstract: Disclosed are methods for reducing transfer pattern defects in a semiconductor device. In some embodiments, a method includes providing a semiconductor device including a plurality of photoresist lines on a stack of layers, wherein the plurality of photoresist lines includes a bridge defect extending between two or more photoresist lines of the plurality of photoresist lines. The method may further include forming a plurality of mask lines by etching a set of trenches in a first layer of the stack of layers, and removing the bridge defect by etching the bridge defect at a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the stack of layers.Type: GrantFiled: July 30, 2020Date of Patent: January 4, 2022Assignee: APPLIED Materials, Inc.Inventors: Regina Freed, Steven R. Sherman, Nadine Alexis, Lin Zhou
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Patent number: 11195718Abstract: Systems and methods for processing a workpiece are provided. In one example, a method includes placing a workpiece on a workpiece support in a processing chamber. The method includes performing a spacer treatment process to expose the workpiece to species generated from a first process gas in a first plasma to perform a spacer treatment process on a spacer layer on the workpiece. The first plasma can be generated in the processing chamber. After performing the spacer treatment process, the method can include performing a spacer etch process to expose the workpiece to neutral radicals generated from a second process gas in a second plasma to etch at least a portion of the spacer layer on the workpiece. The second plasma can be generated in a plasma chamber that is remote from the processing chamber.Type: GrantFiled: June 30, 2020Date of Patent: December 7, 2021Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.Inventors: Tsai Wen Sung, Chun Yan, Hua Chung, Michael X. Yang, Dixit V. Desai, Peter J. Lembesis
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Patent number: 11195714Abstract: A pattern-forming method includes forming a patterned coating film on a part of a surface layer of a base. The surface layer includes regions each of which includes a material that differs from each other. A part of the regions is the part of the surface layer on which the patterned coating film is formed. The patterned coating film includes a first polymer including at an end of a main chain or a side chain thereof a group including a first functional group that is capable of bonding to an atom present in the part of the region. An atom layer is directly or indirectly formed on the surface layer of the base by a vapor deposition, after the forming of the patterned coating film.Type: GrantFiled: July 7, 2020Date of Patent: December 7, 2021Assignee: JSR CORPORATIONInventors: Hitoshi Osaki, Jeffrey Kmiec
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Patent number: 11195723Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.Type: GrantFiled: December 11, 2020Date of Patent: December 7, 2021Assignee: Tokyo Electron LimitedInventors: Shihsheng Chang, David O'Meara, Andrew Metz, Yun Han
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Patent number: 11189492Abstract: A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a base substrate, forming a plurality of discrete core layers on the base substrate, forming an isolation layer on a top surface of a core layer, forming a sacrificial layer on the base substrate and exposing a top surface of the isolation layer, removing the isolation layer after forming the sacrificial layer, removing the sacrificial layer after removing the isolation layer, forming a mask layer on a sidewall surface of the core layer after removing the sacrificial layer, and removing the core layer after forming the mask layer.Type: GrantFiled: September 18, 2020Date of Patent: November 30, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Zhang Pan, Ting Zhang