Abstract: A device for measuring current in a line supplied by a voltage with noise includes a shunt mounted in series in the line, a floating shunt signal amplifier, a floating supply to supply the floating amplifier with a voltage that follows the supply voltage of the shunt, and a differential amplifier whose inputs are connected, on the one hand, to an input terminal of the shunt, and, on the other hand, to the output of the floating amplifier.

Abstract: While a power transistor which is positioned in an upper arm with respect to an inductive load and a power transistor which is positioned in a lower arm are both controlled to be OFF by a controller, reverse currents flowing in current mirror circuits which respectively correspond to these power transistors positioned in the upper arm and the lower arm are detected by current detectors. Since the currents which flow in the current mirror circuits are proportional to the currents which flow in the power transistors provided corresponding thereto, it is possible to detect the load current based upon the reverse currents which are detected by the current detectors.

Abstract: A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.

Abstract: A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of implanted dopants while implanting an initial dose of first conductivity type dopant (e.g., for drain extension regions). The implant blocking layer is then removed and an additional dose of first conductivity type dopant in implanted to form the main source/drain regions. Then, metal is deposited and reacted to form a conductive silicide.

Abstract: A method of testing an integrated circuit includes applying a voltage to one of the pins of the integrated circuit. The pin is floated for a predetermined time. A measurement is performed after the predetermined time. The measurement involves sampling the RC time constant of leakage current of the pins.

Abstract: The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Abstract: A method and apparatus for aligning and connecting objects, such as semiconductor components and substrates, are provided. The apparatus includes a hexapod with a moving platform for holding an object for movement in six degrees of freedom. The apparatus also includes a chuck assembly for holding a mating object in a stationary position. A camera and a height gauge are mounted on the moving platform to allow determination of the position and orientation of the object on the chuck assembly. Likewise, a camera and a height gauge are mounted on the chuck assembly to allow determination of the position and orientation of the object on the moving platform. The hexapod includes-linear actuators operable by a controller upon signal input from the cameras and height gauges. The apparatus can be used. to electrically connect semiconductor dice and chip scale packages to interconnects for testing.

Abstract: An integrated circuit chip can be thermally destroyed in a tester due to a defective pressed joint with a temperature regulating component. A method which prevents such destruction begins with the step of maintaining the chip at one temperature while forcing the temperature regulating component to a different temperature, when the chip and the temperature regulating component are spaced apart in the tester. Next, the chip at its one temperature and the temperature regulating component at its different temperature are pressed together. Then a temperature change is sensed in either the chip or the temperature regulating component, during a time interval that begins when the temperature regulating component and the chip initially press together. Thereafter, electrical power is applied to the chip in the tester only if the temperature change, which is sensed by the sensing stop, meets a predetermined criteria.

Abstract: A semiconductor-wafer chuck for heating and cooling a device-under-test includes a heat-spreader plate with a clamping surface for a semiconductor wafer. A heater is disposed within the heat-spreader plate. A chiller heat-exchanger provides for heat removal. A motion control system is used to move the chiller heat-exchanger in relation to the heat-spreader plate, and thus provide for an adjustment of the thermal resistance and thermal coupling between the two. The heater comprises electric heating elements with a variable power input, and the chiller heat-exchanger is moved sufficiently far away to prevent boiling and evaporation of a coolant disposed inside. A device-under-test temperature controller controls the device-under-test temperature by adjusting the heater power, chiller fluid temperature and/or by moving the chiller heat-exchanger in relation to the heat spreader plate.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A probe card assembly that compensates for differing rates of thermal expansion is disclosed herein. The assembly is comprised of a multi-layered dielectric plate interposed between a probe head and a printed circuit board. The printed circuit board has arrayed upon its surface a first plurality of electrical contacts arranged in a pattern. The dielectric plate has a second plurality of electrical contacts arranged in a pattern matching the first plurality of contacts. A planarizing interposer is interposed between the plate and the printed circuit board and has a pattern of holes matching the pattern of electrical contacts on the printed circuit board and plate. The assembly further includes a plurality of electrical connectors disposed within each of the holes arrayed in a pattern upon the planarizing interposer a plurality conductive bumps or fuzz buttons making electrical contact with the first and second plurality of electrical contacts.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.

Abstract: A vortex unit suitable for providing a desired environment for a semiconductor process may include a vortex tube and a semiconductor processing device suitable for performing a semiconductor processing function. The vortex tube includes an air inlet for receiving compressed air, a first air exhaust for outputting an air stream having a temperature greater than the received compressed air, and a second air exhaust for outputting an air stream having a temperature lower than the received compressed air. The semiconductor processing device is connected to the second air exhaust of the vortex tube so that the semiconductor processing device receives a cooled air stream from the vortex tube, the cooled air stream providing an environment suitable for enabling the semiconductor processing device to perform the semiconductor processing function.

Abstract: A current sensor arrangement for measuring electrical current flow (subject flow) includes an elongated conductor for carrying the subject flow through a region. A magnetic field sensing device is located in the region, and produces a sensed voltage representative of the magnitude of the magnetic field in the region. A test generator generates a magnetic field component having “known” magnitude in the spatial region. The test generator is gated, so that the magnetic field changes when the test generator is ON. If the test generator generates its magnetic field by passing a test current through the spatial region, the change in the magnetic field, which is expressed in the sensed voltage, is related to the test current. Simple control circuit processing determines the subject current from the sensed magnetic field and the known magnitude of the test current.

Abstract: A non-destructive and non-intrusive, user friendly, easy to setup and efficient system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications is provided. Additionally, the present invention determines the gate oxide thickness when the operational MOSFET is operating in the inversion mode.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: Integrated circuit die on a wafer are tested individually, without probing any of the die, using circuitry (TC1-8, BC1-8, LR1-8, RR1-8, PA1-PA4) provided on the wafer. The process connects first and second bond pads of a first die to provide a test path through the first die. The process applies a test signal to a second die connected to the second bond pad of the first die. The process passes the test signal from the first bond pad of the first die along the test path through the first die to the second bond pad of the first die and then to the second die.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.