Abstract: A method for fabricating a semiconductor device includes a step of depositing a first compound semiconductor layer by a MOVPE process to have a first conductivity type, doping a surface of the first compound semiconductor layer to the same, first conductivity type, by implementing a planar doping process as a result of decomposition of a gaseous dopant, such that no substantial growth of the first compound semiconductor layer occurs during the planar doping process, and depositing a second compound semiconductor layer of the first conductivity type on the doped surface of the first compound semiconductor layer by a MOVPE process.

Abstract: The optical response of high-quality epitaxial copper-oxide perovskite films on substrates such as LaGaO.sub.3 and SrTiO.sub.3 exhibits a nonbolometric component to a photoresponse at certain temperatures below the onset of the superconducting transition and when carrying bias currents of a certain magnitude. A nonbolometric superconductive photoresponsive cell and method employ such films. The photoresponsive cell and method of the invention can be used to detect electromagnetic radiation incident on the film and to switch or modulate electrical signals passing through the film.

Abstract: A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. the via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies 335a, 335b, 335c with conductive vias are stacked on top of each other. Other dies 341, 343 are connected together with an optical coupling die 342.

Abstract: This is a highly purified metal comprising one metal selected from the group consisted of titanium, zirconium and hafnium. The highly purified metal has an Al content of not more than 10 ppm. It also has an oxygen content of more than 250 ppm, each of Fe, Ni and Cr contents not more than 10 ppm and each of Na and K contents not more than 0.1 ppm. The highly purified metal is obtained by either purifying crude metal by the iodide process or surface treating crude metal to remove a contaminated layer existing on the surface thereof and then melting The surface treated material with electron bean in a high vacuum.

Abstract: Quantum well detector, in which the active detection zone (2) occupies only a limited area of the device and in which a diffraction grid (5) having a larger surface area than this zone thereby makes it possible to couple to it a greater light flow than that corresponding to the surface area of this zone. In this way, the sensitivity of the device is increased.Application: Detection of optical radiation.

Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.

Abstract: A semiconductor arrangement with a vertical power semiconductor switch and an integrated CMOS or bipolar circuit is provided, whereby the integrated CMOS or bipolar circuit is arranged on a semiconductor islet insulated from a first semiconductor material region by a buried insulating layer. The first semiconductor material region is included as a part of the structure of the power semiconductor switch. The buried insulating layer is surrounded by a second semiconductor material region arranged between it and the first semiconductor material region, the doping of which is the opposite of that of the first semiconductor material region. The second semiconductor region is coupled to the first semiconductor region by a circuit. This circuit does not directly connect the potential of the second semiconductor material region with the potential of the first semiconductor material region.

Abstract: It is an object to downsize a device while maintaining a high breakdown voltage. An external terminal (7) protrudes to the outside from the side wall of a sealing resin (2) and a heat sink (1) is exposed in the bottom of the sealing resin (2). A step surface (21) retracted from the exposed surface of the heat sink (1) is formed in the part of the sealing resin (2) surrounding the periphery of the heat sink (1). When using this semiconductor device, the exposed surface of the heat sink (1) is brought into surface contact with the flat surface (41a) of the radiation fin (41) and an insulation sheet (31) is interposed between the step surface (21) and the flat surface (41a), and which is pressed therebetween. The insulation sheet (31) is disposed to cover the region facing the external terminal (7) in the flat surface (41a).

Abstract: A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.

Abstract: An electronic device which includes, a couple of first conduction regions which are capable of confining carriers, a second conduction region having a higher energy level than those of the first conduction regions, and a first electrode for impressing a voltage on the first conduction regions, wherein when a voltage is impressed via the first electrode between the couple of first conduction regions, carriers are caused to move due to a tunneling effect from one of the first conduction regions via the second conduction region to the other of the first conduction regions, and when the voltage impressed between the couple of first conduction regions is removed, carriers are confined mainly in the one of the first conduction regions.

Abstract: The invention provides a semiconductor device in the form of an LSI circuit having a large number of terminals wherein an increase of the number of pad terminals for a power source potential and wherein a ground potential does not increase the inductances of wiring lines to the pad terminals and the terminals are arranged efficiently. The semiconductor device includes a semiconductor chip having a semiconductor substrate on which a first pad arrangement region, a buffer arrangement region and a second pad arrangement region are successively assured in this order toward the outer side around an internal circuit formation region and arranged in parallel to each other. A first power source pad and a first grounding pad for an internal circuit are provided in the first pad arrangement region while a plurality of pads for inputting and/or outputting signals are provided in the second pad region. The pads are bonding connected by respective thin metal lines to external lead terminals provided on a support.

Abstract: A high voltage protection circuit includes breakdown networks for providing a discharge path between a pair of terminals of a circuit to be protected. Each network conducts current between a supply terminal and another terminal at a low threshold voltage value when power is removed from the supply terminal. The network increases the threshold value when power is applied to the supply terminal to prevent conduction through the breakdown network during normal operation of the circuit to be protected. In one implementation, the protection circuit includes anti-latching circuitry connected to the breakdown network for preventing the breakdown network from latching on after or during the time power is applied to the supply terminals. To minimize the degradation of DC operating characteristics, the leakage currents, due to the protection circuit, between the first terminal and the positive supply terminal, and between the first terminal and the negative supply terminal cancel each other.

Abstract: A cold cathode device is provided comprising a wide-bandgap (>5 eV) material exhibiting negative electron affinities, low trap densities, and high carrier mobilities, a junction between a first region of the wide-bandgap material having n-type conductivity and a second region of the wide-bandgap material having p-type conductivity, and a conductive contact to forward bias the junction causing electrons to be emitted near the junction into an exterior region.

Abstract: A semiconductor device has a structure in which doped layers and undoped layers are alternately stacked and is constituted by (a) a semi-insulating substrate, (b) undoped layers consisting of a substantially undoped diamond material, and (c) thin doped layers formed between the undoped layers and consisting of a diamond material doped with B as an impurity. Stable operation characteristics can be obtained within a temperature range from room temperature to a high temperature while a semiconductor material having a deep impurity level is used.

Abstract: A semiconductor integrated circuit comprises a conductive protein electrode, such as cytochrome c, deposited on the surface of an apatite insulating layer such as hydroxyapatite, fluorinated apatite or chlorinated apatite. The apatite insulating layer is thin film coated onto a substrate such that it is substantially C-axis (002) oriented, which allows the integrated circuit to be of small size while minimizing undesired electron transfer between electrodes because the conductive protein electrode adopts the orientation of the apatite insulating film.

Abstract: A surface mountable integrated circuit is disclosed. Dies 1041 with edge connections 1080 are coupled to each other with the edge connection and to a printed circuit board 1070.

Abstract: The i-type semiconductor layer (AS) and the gate insulating film (GI) are patterned along and in the same shape as the video signal lines (DL) between the video signal lines (DL) and the first transparent glass substrate (SUB1). The backlight is disposed on the second transparent glass substrate (SUB2) side. Therefore, signal line reflection of external light can be prevented, improving the display quality.

Abstract: A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.

Abstract: A bipolar transistor in which the emitter possesses a double "mesa" structure so as to achieve the maximum avoidance of the phenomena of electron/hole recombinations that have a deleterious effect on the current gain. The double mesa emitter can be made out of an alternation of materials M.sub.I /M.sub.II having different types of behavior with respect to a pair of etching methods. These materials may be GaInP and GaAs.

Abstract: A semiconductor device wherein an effective surface area is secured within a contact hole and wherein a storage electrode with rectangular corners is exactly patterned. The effective surface area within a contact hole can be obtained by overlapping the storage electrode contact hole with a portion of the storage electrode, so as to ensure more capacitance. Rounding of the corner of the rectangular storage electrode, which directs the resulting storage electrode to diminish in effective surface area, can be prevented by the different position of the storage electrode mask at the contact hole from one row or column to next, so as to make no difference between the patterned storage electrode and the designed one.