Patents Examined by Sara W. Crane
  • Integrated electro-optical package and method of fabrication
    Patent number: 5708280
    Abstract: An integrated electro-optical package including a dual sided opto-electronic device, composed of a substrate with an array of light emitting devices (LEDs) formed on a first major surface thereof, and at least one vertical cavity surface emitting laser formed on an opposed second major surface of the substrate. A mounting structure formed so as to allow for the mounting of the dual sided opto-electronic device on the interior major surfaces, and further having electrical conductors for cooperating with the LEDs and VCSEL of the opto-electronic device. A driver substrate having electrical connections for interfacing with the mounting structure and the dual sided opto-electronic device. A plurality of driver circuits connected to the mounting structure and dual sided opto-electronic device through connection pads formed on the driver substrate.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: January 13, 1998
    Assignee: Motorola
    Inventors: Michael S. Lebby, Wenbin Jiang, Karen E. Jachimowicz
  • Non-volatile random access memory
    Patent number: 5708284
    Abstract: A non-volatile random access memory comprises a memory cell including: a MOS transistor having a gate insulation film formed on a semiconductor substrate, a gate electrode, and a pair of impurity diffusion layers; and an MFS transistor having at least a bottom gate electrode, a ferroelectric film, a top electrode, and a pair of impurity diffusion layers, one of the impurity diffusion layers of the MFS transistor being shared with the MOS transistor and connected to a portion of the bottom gate electrode; wherein the MOS transistor is connected to a bit line and a word line, and the MFS transistor is connected to a drive line and a common source line.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: January 13, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shigeo Onishi
  • Non-volatile semiconductor information storage device
    Patent number: 5708285
    Abstract: A non-volatile semiconductor storage device with which a multi-value memory is realized and the amount of information storable is increased without increasing the number of memory transistors and the area occupied thereby. A gate electrode portion 20a of each memory transistor has a two-layer floating gate structure comprising two floating gate electrodes 22a, 22b and a control gate electrode 24 which are substantially vertically laminated one above another. The non-volatile semiconductor storage device is thereby constructed as a multi-value memory capable of providing a state "1" where electrons are injected into the first floating gate electrode 22a, a state "0" where electrons are injected into the first and second floating gate electrodes 22a, 22b, and a state "2" where electrons are withdrawn from the first and second floating gate electrodes 22a, 22b.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: January 13, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoko Otani, Toshiharu Katayama
  • Increased efficiency LED
    Patent number: 5705834
    Abstract: In an LED a large portion of the light produced is lost due to total internal reflection at the air-semiconductor interface. A reverse taper of the semiconductor is used to change the angle at which light strikes the interface so that a greater portion of the light is transmitted.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: January 6, 1998
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Claudio O. Egalon, Robert S. Rogowski
  • Semiconductor device comprising an SiOF insulative film
    Patent number: 5703404
    Abstract: A semiconductor device having an interlayer insulating film improved to decrease film shrinkage and film stress is provided. Metal interconnections are formed on a substrate. A silicon oxide film is provided on the substrate to cover the metal interconnections and to fill a space between the metal interconnections. The chemical formula of the silicon oxide film contains Si-F bond.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: December 30, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masazumi Matsuura
  • Method for preparation of conjugated arylene or heteroarylene vinylene polymer and device including same
    Patent number: 5700696
    Abstract: A technique is described for the preparation of conjugated arylene and heteroarylene vinylene polymers wherein conversion of the polymer precursor is effected at a temperature ranging from 150.degree.-300.degree. C. in the presence of forming gas. Studies have shown that the presence of the forming gas suppresses the formation of carbonyl groups, so resulting in an enhancement in photoluminescence and electroluminescence efficiency of the polymer.
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: December 23, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Edwin Arthur Chandross, Mary Ellen Galvin-Donoghue, Fotios Papadimitrakopoulos
  • Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit
    Patent number: 5701037
    Abstract: In an arrangement for signal transmission between chip layers of a vertically integrated circuit, a defined, inductive signal transmission ensues between a part of the vertically integrated circuit in one chip layer and a further part of the vertically integrated circuit in a further chip layer by means of a coupling inductance formed by respective coils in the two layers. Particularly given high connection densities, a large number of freely placeable and reliable vertical signal connections can be produced directly from the inside of one chip layer to the inside of a neighboring chip layer without extremely high demands being made on the adjustment of the chip layers relative to one another and on the surface planarity of the individual chip layers.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: December 23, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventors: Werner Weber, Stefan Kuehn, Michael Kleiner, Roland Thewes
  • Light-emitting diode
    Patent number: 5698865
    Abstract: The light-emitting diode consists of a substrate and a light-emission-generating layer located on the substrate and embedded between the cladding layers of a double heterostructure. On the top cladding layer, a current diffusion layer is located on which there is a further contact layer structure. The current diffusion layer is sufficiently thin so as to hardly absorb any light-emission. Thus, it can be economically produced by means of the MOCVD process. At the same time, the contact layer structure is provided with branched and finger-type electrodes for distributing the current together with the current diffusion layer onto the surface of the light-emission-generating layer. However, the structural size of the branched and finger-type electrodes is selected such that these can still be manufactured by the standard processes used in LED manufacture.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: December 16, 1997
    Assignee: Temic Telefunken microelectronic GmbH
    Inventors: Jochen Gerner, Klaus Gillessen
  • Field effect transistor device with single layer integrated metal and retained semiconductor masking
    Patent number: 5698900
    Abstract: A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor layer and includes a permanent semiconductor material-comprised secondary mask element, a mask element which can be grown epitaxially during wafer fabrication to perform useful functions in both the device processing and device utilization environments. The device of the invention may be achieved with both an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed device provides a field-effect transistor of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: December 16, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Christopher A. Bozada, Tony K. Quach, Kenichi Nakano, Gregory C. DeSalvo, G. David Via, Ross W. Dettmer, Charles K. Havasy, James S. Sewell, John L. Ebel, James K. Gillespie
  • High electron mobility transistor (HEMT) and pseudomorphic high electron mobility transistor (PHEMT) devices with single layer integrated metal
    Patent number: 5698870
    Abstract: A periodic table group III-IV HEMT/PHEMT field-effect transistor device and its fabrication is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photoresponsive secondary mask element affording several practical advantages during fabrication and in the completed transistor. The invention includes provisions for both an all-optical lithographic fabrication process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: December 16, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Kenichi Nakano, Christopher A. Bozada, Tony K. Quach, Gregory C. DeSalvo, G. David Via, Ross W. Dettmer, Charles K. Havasy, James S. Sewell, John L. Ebel, James K. Gillespie
  • Semiconductor device and method for manufacturing the same
    Patent number: 5698891
    Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces and including a denuded zone, in which an oxygen concentration is lower than that in an inner portion of the semiconductor substrate and which does not include a bulk microdefect, and an intrinsic gettering zone, an element region formed on the first surface of the semiconductor substrate, and an extrinsic gettering layer, made of an amorphous semiconductor material which traps a metal impurity, and formed directly on at least a portion of the intrinsic gettering region or the denuded zone entirely or partially thinned of the second main surface of the semiconductor substrate.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Mami Saito, Kikuo Yamabe
  • Semiconductor device
    Patent number: 5696386
    Abstract: A method relates to fabrication of semiconductor devices such as TFTs on an insulating substrate. After forming a coating consisting mainly of aluminum nitride, semiconductor devices such as TFTs or semiconductor integrated circuits comprising said semiconductor devices are built directly or indirectly on the coating to form e.g. an active matrix liquid crystal display. A coating consisting mainly of silicon oxide may be formed on the coating consisting mainly of aluminum nitride and under said semiconductor devices or said semiconductor integrated circuits.
    Type: Grant
    Filed: February 9, 1994
    Date of Patent: December 9, 1997
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventor: Shunpei Yamazaki
  • Input protection circuit and method of fabricating semiconductor integrated circuit
    Patent number: 5696397
    Abstract: The present invention provides an input protection circuit including a first MOS FET including a source electrically connected to an input terminal and a drain and a gate both electrically connected to a grounding line, a second MOS FET including a source electrically connected to the input terminal and a drain and a gate, and a third MOS FET including a source electrically connected to a power line and a drain and a gate to both of which are electrically connected a drain and a gate of the second MOS FET. The input protection circuit shares a parasitic p-MOS transistor with an internal circuit, and hence it is no longer necessary to form a parasitic MOS transistor to be used only for an input protection circuit. Thus, the input protection circuit decreases the number of photomask using steps by one relative to a conventional protection circuit.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: December 9, 1997
    Assignee: NEC Corporation
    Inventor: Isami Sakai
  • System having input-output drive reduction
    Patent number: 5696403
    Abstract: An electronic system utilizing at least one integrated circuit that has reduced drive requirements for the input and output pads of the integrated circuit die. The integrated circuit of the system has an intermediate structure added between the output connection pad and substrate to reduce the amount of electron charge required to charge the output pad capacitance of the integrated circuit to a substantially negligible amount. In addition, an intermediate structure may be added between an input connection pad and substrate of the integrated circuit to reduce the amount of electron charge required to charge the input pad capacitance to a substantially negligible amount.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: December 9, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch
  • MOS-type semiconductor integrated circuit device
    Patent number: 5696400
    Abstract: A semiconductor integrated circuit device comprises an input terminal for inputting a voltage, an output terminal for outputting a voltage, a MOS driver disposed between the input terminal and the output terminal for adjusting the voltage of the input terminal and transmitting it to the output terminal, and a MOS control circuit for controlling the MOS driver and feeding back voltage information of the output terminal. Each of the MOS driver and the MOS control circuit has a MOS transistor formed on a semiconductor substrate, and each MOS transistor has a source region, a drain region, a channel region disposed between the source region and the drain region, a gate insulating film disposed over the channel region, and a gate electrode disposed over the gate insulating film. The gate insulating films of the MOS transistors have different film thicknesses.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: December 9, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Shinichi Yoshida, Yutaka Saitoh, Jun Osanai
  • Integrated circuitry having a pair of adjacent conductive lines
    Patent number: 5691565
    Abstract: A method of forming integrated circuitry includes, a) providing a pair of spaced and adjacent electrically conductive elongated lines; and b) providing electrically insulative material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. Preferably, the electrically insulative material is provided by depositing electrically insulative material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at at least one end. The void at the one end is subsequently sealed.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: November 25, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Electrostatic discharge protection circuit triggered by capacitive-coupling
    Patent number: 5686751
    Abstract: An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load. The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit V.sub.SS /V.sub.DD. A gate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor. The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the V.sub.SS /V.sub.DD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: November 11, 1997
    Assignee: Winbond Electronics Corp.
    Inventor: Chau-Neng Wu
  • Semiconductor memory device provided with capacitors formed above and below a cell transistor
    Patent number: 5684316
    Abstract: A semiconductor memory device provided with capacitors formed above and below a cell transistor includes first and second transistors formed in a first level, a first storage electrode connected to the first transistor and formed below the first level, and a second storage electrode connected to the second transistor and formed above the first level. The first and second storage electrodes are connected to each source via a spacer formed on the sidewalls of each source, and undercuts are formed between the storage electrode and the transistor, to thereby obtain double or more cell capacitance, a stable cell transistor characteristic and reduced short-channel effects.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: November 4, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joo-young Lee
  • Vertical precharge structure for DRAM
    Patent number: 5684313
    Abstract: A DRAM one device cell and an associated precharge circuit are integrated together in a novel structure having an area of only four square features. The structure also provides physical and electrical separation between adjacent cells along a direction parallel to the DRAM word lines. The DRAM bit line length per bit is reduced by 50% relative to a conventional planar integrated structure disclosed elsewhere. As a result, bit line capacitance is also substantially reduced, and the effectiveness of a precharge technique for reduction of DRAM power consumption is enhanced by the dense novel structure.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: November 4, 1997
    Inventor: Donald M. Kenney
  • Electrochemical light-emitting devices
    Patent number: 5682043
    Abstract: Electrochemical light emitting devices are disclosed which include a composite material in contact with two electrodes. The composite material is an admixture of ionic species and an `immobile` semiconductor. The semiconductor is capable of supporting both p- and n-type carriers and having a doping profile which can be dynamically changed in a controlled fashion through reversible electrochemical oxidation and reduction. Devices having this structure may be used to generate electrochemically induced p-n junctions, thereby providing a new means of exploiting the light emitting properties of such junctions under an applied voltage. Systems and methods for generating useful levels of light employing these devices are also disclosed.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: October 28, 1997
    Assignee: Uniax Corporation
    Inventors: Qibing Pei, Floyd L. Klavetter