Abstract: An imaging device includes a semiconductor substrate including a semiconductor region including an impurity of a first conductivity type, a first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type, and that converts incident light into charges, and a second diffusion region that includes an impurity of the second conductivity type and that accumulates at least a part of the charges flowing from the first diffusion region, a first transistor that includes a first gate electrode and that includes the second diffusion region as one of a source and a drain, a contact plug electrically connected to the second diffusion region, a capacitive element one end of which is electrically connected to the contact plug, and a second transistor that includes a second gate electrode, the second gate electrode being electrically connected to the one end of the capacitive element.

Abstract: A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer (101) and a buffer layer (102), of a buffer material different from a material of the wafer, the buffer layer having a growth surface (1021); an array of nano structures (1010) epitaxially grown from the growth surface; a continuous planar layer (1020) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer (1030), epitaxially grown on the planar layer (1020).

Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, a flexible display panel, and a display device, all for achieving a frame-free full-screen flexible display product. The array substrate provided in the present disclosure comprises a flexible base substrate, a thin film transistor on a first surface of the flexible base substrate, and a wiring terminal for transmitting a signal to an electrode of the thin film transistor on a second surface of the flexible base substrate opposite to the first surface. The electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate.

Abstract: Variations in photoelectric conversion performance between pixels (valid pixels and light-shielding pixels) in an imaging element are reduced.

Abstract: Provided is a heat flow switching element which has a larger change in a thermal conductivity and has excellent thermal responsiveness. The heat flow switching element includes an N-type semiconductor layer, an insulator layer laminated on the N-type semiconductor layer, a P-type semiconductor layer laminated on the insulator layer, an N-side electrode connected to the N-type semiconductor layer, and a P-side electrode connected to the P-type semiconductor layer. In particular, the insulator layer is formed of a dielectric. Also, a plurality of N-type semiconductor layers and P-type semiconductor layers are laminated alternately with the insulator layer interposed therebetween.

Abstract: A solid-state imaging device includes a semiconductor layer, an insulating layer, a plurality of photodetection elements, a transistor, and a metal member. The insulating layer is provided on the semiconductor layer. The photodetection elements are provided in the semiconductor layer, and arranged in a line. The photodetection elements generate charges at light incidence. The transistor is provided in an amplifier circuit. The amplifier circuit is provided in the semiconductor layer and the insulating layer, is isolated from the photodetection elements, and amplifies electrical signals due to the charges. The metal member is disposed between a photodetection area and the transistor in a plan view. The photodetection area is provided with the photodetection elements.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

Abstract: A new transistor structure is disclosed. This new structure has a dielectric stress layer in a three-dimensional structure outside of the gate region for modulation or the characteristics of the transistor. Additionally, trenches are created in the region between the source electrode and the drain electrode in such a manner so as to create ridges that traverse the gate region.

Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.

Abstract: A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

Abstract: A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

Abstract: Provided is a semiconductor element including: a front-back conduction-type substrate including a front-side electrode and a back-side electrode; and an electroless plating layer formed on at least one of the electrodes of the front-back conduction-type substrate. The electroless plating layer includes: an electroless nickel-phosphorus plating layer; and an electroless gold plating layer formed on the electroless nickel-phosphorus plating layer, and has a plurality of recesses formed on a surface thereof to be joined with solder.

Abstract: Disclosed herein are a radiation detector and a method of making it. The radiation detector is configured to absorb radiation particles incident on a semiconductor single crystal of the radiation detector and to generate charge carriers. The semiconductor single crystal may be a CdZnTe single crystal or a CdTe single crystal. The method may comprise forming a recess into a substrate of semiconductor; forming a semiconductor single crystal in the recess; and forming a heavily doped semiconductor region in the substrate. The semiconductor single crystal has a different composition from the substrate. The heavily doped region is in electrical contact with the semiconductor single crystal and embedded in a portion of intrinsic semiconductor of the substrate.

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate includes a base substrate; a first metal layer on the base substrate; a first insulating layer on the first metal layer; a second metal layer on the first insulating layer; and a second insulating layer located on the second metal layer. The array substrate includes a display region and a peripheral region surrounding the display region, the first metal layer includes a plurality of signal lines in the peripheral region, the second insulating layer includes at least one groove overlapping at least two signal lines, the second metal layer includes a metal strip in the peripheral region, and in the area where the groove overlaps the signal lines, an orthographical projection on the base substrate fall into the orthographic projection of the metal strip on the base substrate.

Abstract: An alignment mark includes an alignment region, a peripheral region and a shielding region. The alignment region has an outer contour; the peripheral region is disposed around at least a part of the outer contour of the alignment region; the shielding region is disposed around at least a part of the outer contour of the alignment region and is non-overlapped with the peripheral region; and the alignment region and the shielding region are opaque, and the peripheral region is at least partially transparent.

Abstract: An organic light-emitting diode (OLED) substrate includes: a base substrate including a display region having a plurality of luminous regions and a non-luminous region separating one or more adjacent luminous regions, the non-luminous region including a plurality of first connection regions; a first electrode layer over the base substrate including a plurality of first electrodes having their projections on the base substrate cover the plurality of luminous regions; a pixel defining layer over the first electrode layer and located at the non-luminous region and defining the plurality of luminous regions, the pixel defining layer is hollowed out at the first connection regions; an electroluminescent functional layer provided over the pixel defining layer; a second electrode layer over the electroluminescent functional layer; and a plurality of conductive structures located at the plurality of first connection regions respectively, and electrically coupled to the second electrode layer.

Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer, and forming a tri-layer gate having a gate foot in the first opening, a gate neck extending from the gate foot, and a gate head extending from the gate neck. The gate foot has a first width, and the gate neck has a second width that is wider than the first width. The gate neck extends for a length over the dielectric passivation layer on both sides of the first opening. The gate head has a third width wider than the second width of the gate neck.

Abstract: A light emitting device for a display including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, electrode pads disposed below the first LED sub-unit, and a filler disposed between the electrode pads, in which the electrode pads include a common electrode pad electrically connected in common to the first, second, and third LED sub-units, and first, second, and third electrode pads connected to the first, second, and third LED sub-units, respectively, the first, second, and third LED sub-units are independently drivable, light generated in the first LED sub-unit is configured to be emitted to the outside of the light emitting device through the second and third LED sub-units, and light generated in the second LED sub-unit is configured to be emitted to the outside through the third LED sub-unit.