Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

Abstract: A semiconductor device comprises a plurality of stacking blocks and a plurality of conductive lines. Each stacking blocks comprises two opposite finger VG structures. Each finger VG structure includes a staircase structure and a plurality of bit line stacks. The staircase structure is perpendicular to the bit line stacks, and the bit line stacks of the two opposite finger VG structures are arranged alternately. The conductive lines is disposed over the stacking blocks at interval. The direction of the conductive lines is parallel to a direction of the bit line stacks. The conductive lines include a plurality of bit lines and a plurality of ground lines, and each stacking block includes at least one ground line.

Abstract: The present disclosure provides one embodiment of a motion sensor structure. The motion sensor structure includes a first substrate having an integrated circuit formed thereon; a second substrate bonded to the first substrate from a first surface, wherein the second substrate includes a motion sensor formed thereon; and a third substrate bonded to a second surface of the second substrate, wherein the third substrate includes a recessed region aligned with the motion sensor.

Abstract: Described is a solid-state light-emitting element, a light-emitting device using the solid-state light-emitting element, and a lighting device using the light-emitting device. The solid-state light-emitting element comprises a member with a low refractive index which has a hemispherical structure on a first surface and an uneven structure on a second surface, a bonding layer with a high refractive index which planarizes the uneven structure, and a light-emitting body whose light-emitting surface is in contact with a flat surface of the bonding layer. The uneven structure of the member with a low refractive index is provided inside at least an outside shape of the hemispherical structure formed on the first surface; and the light-emitting body is provided such that an outside shape of the light-emitting region of the light-emitting body is smaller than the outside shape of the hemispherical structure and overlaps with the hemispherical structure.

Abstract: A light-reflective conductive particle for an anisotropic conductive adhesive used for anisotropic conductive connection of a light-emitting element to a wiring board includes a core particle coated with a metal material and a light-reflecting layer formed from light-reflective inorganic particles having a refractive index of 1.52 or more on a surface of the core particle. Examples of the light-reflective inorganic particles having a refractive index of 1.52 or more include titanium oxide particles, zinc oxide particles, or aluminum oxide particles.

Abstract: A highly reliable semiconductor device is provided. A semiconductor device is manufactured at a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, an oxide semiconductor film containing indium, and an insulating layer provided on and in contact with the oxide semiconductor film so as to overlap with the gate electrode layer are stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the insulating layer, the chlorine concentration and the indium concentration on a surface of the insulating layer are lower than or equal to 1×1019/cm3 and lower than or equal to 2×1019/cm3, respectively.

Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.

Abstract: Provided is a graphene switching device including: a graphene layer formed on a substrate; a plurality of semiconductor nanowires on the substrate; a first electrode connected to a second end of the graphene layer; a second electrode on the substrate to face the first electrode so as to be connected to the plurality of semiconductor nanowires; a gate insulating layer on the substrate to cover the graphene layer; and a gate electrode on the gate insulating layer. The gate electrode and the plurality of semiconductor nanowires face each other with the graphene layer therebetween. At least one of the plurality of semiconductor nanowires is connected to at least one of the second electrode, the graphene layer, and the other of the plurality of semiconductor nanowires.

Abstract: A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid HCl in gaseous form and dichlorosilane DCS in gaseous form, so that the ratio between the amount of HCl and the amount of DCS has a value of from 3.5 to 5.5.

Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Abstract: A light emitting device is provided, which includes an n-type layer, a p-type layer, and an active region sandwiched between the n-type layer and the p-type layer. The active-region includes one or more quantum wells each sandwiched by quantum barriers, at least one of the quantum wells has a polarization induced electric field equal to or greater than 106 V/cm, and at least one of the quantum barriers adjacent to the at least one of the quantum wells is doped to generate a PN junction maximum electric field equal to or greater than the polarization induced electric field to substantially cancel out the polarization induced electric field within the at least one of the quantum wells.

Abstract: A light emitting apparatus includes an electrically insulating base member having a longitudinal direction; a pair of electrically conductive pattern portions formed on an upper surface of the base member; at least one light emitting device that is electrically connected to the pair of electrically conductive pattern portions; and a resin portion that surrounds at least a side surface of the at least one light emitting device with at least an upper surface of the at least one light emitting device being exposed from the resin portion and partially covers the pair of electrically conductive pattern portions. Each of the pair of electrically conductive pattern portions extends toward a periphery of the base member from resin-covered parts of the electrically conductive pattern portions. Each of the electrically conductive pattern portions forms a narrower area and a wider area in the longitudinal direction.

Abstract: Disclosed are a light-emitting device and a manufacturing method thereof. A light-emitting device according to an exemplary embodiment of the present invention includes a base, a lighting element disposed on the base, the lighting element including an epitaxial layer and a substrate disposed on the epitaxial layer, a contact member disposed between the lighting element and the base, the contact member electrically connecting the lighting element and the base, and a lens disposed on the substrate.

Abstract: This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

Abstract: A semiconductor device. The device including a substrate having electrical traces, at least one of a MEMS die and a semiconductor chip mounted on the substrate, and a spacer. The spacer has a first end connected to the substrate and includes electrical interconnects coupled to the electrical traces. The at least one MEMS die and a semiconductor chip are contained within the spacer. The spacer and substrate form a cavity which contains the at least one MEMS die and a semiconductor chip. The cavity forms an acoustic volume when the semiconductor device is mounted to a circuit board via a second end of the spacer.

Abstract: Disclosed are a light-emitting device and a manufacturing method thereof. A light-emitting device according to a preferred embodiment of the disclosure comprises: a frame portion having a bottom and a sidewall; a light-emitting portion which is disposed on the frame portion and emits light; and a window portion disposed over the frame portion so as to cover the light-emitting portion.