Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the channel material is different from the lattice constant of the bulk substrate to introduce strain to the channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.

Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

Abstract: Systems and methods of manufacturing compact camera assemblies for use in electronic device are provided. The camera assemblies include an image sensor and a camera component. The camera assemblies further include a molding compound transfer molded onto the image sensor and the camera component to form a camera component subassembly. A redistribution layer is formed on a surface of the camera component subassembly. The redistribution layer includes at least one dielectric layer and a first interconnect layer. The camera assemblies further include a lens module coupled to the redistribution layer and aligned with the image sensor along an optical axis.

Abstract: A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

Abstract: A method of manufacturing a Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, and part of the upper layer is exposed from an isolation insulating layer. A gate structure is formed over part of the fin structure. An amorphous layer is formed over the gate structure and the fin structure not covered by the gate structure. A recrystallized layer is formed by partially recrystallizing the amorphous layer over the fin structure not covered by the gate structure. A remaining amorphous layer which is not recrystallized is removed. Source and drain electrode layers are formed over the recrystallized layer.

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

Abstract: Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.

Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Abstract: A graphite substrate is processed to have surface unevenness in a range of 1 ?m to 8 ?m. Thereby, a semiconductor film to be laminated on the graphite substrate has a stable film quality, and thus adhesion of the graphite substrate and the semiconductor layer can be enhanced. When an electron blocking layer is interposed between the graphite substrate and the semiconductor layer, the electron blocking layer is thin and thus the surface unevenness of the graphite substrate is transferred onto the electron blocking layer. Consequently, the electron blocking layer also has surface unevenness approximately in such range. Thus, almost the same effect as a configuration in which the semiconductor layer is directly connected to the graphite substrate can be produced.

Abstract: A non-volatile memory device may include a first well of a first conductive type formed over a substrate, a second well of a second conductive type formed over the substrate to contact the first well, a trench formed over the substrate on a border formed by the contact of the first well and the second well, and a memory gate having a memory layer formed over a surface of the trench, and a gate electrode formed to fill the trench over the memory layer.

Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

Abstract: An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an etchant to remove the sacrificial material layers to form lateral recesses and to provide a reactant for depositing electrically conductive layers in the lateral recesses. By distributing the access openings across the entirety of the openings and eliminating the need to employ backside trenches for replacement of the sacrificial material layers, the size and lateral extent of backside trenches can be reduced to a level sufficient to accommodate only backside contact via structures.

Abstract: Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.

Abstract: It is an object to provide a display device of which image display can be favorably recognized. Another object is to provide a manufacturing method of the display device with high productivity. Over a substrate, a pixel electrode that reflects incident light through a liquid crystal layer, a light-transmitting pixel electrode, and a structure whose side surface is covered with a reflective layer and which is positioned to overlap with the light-transmitting pixel electrode are provided. The structure is formed over a light-transmitting etching-stop layer, and the etching-stop layer remains below the structure as a light-transmitting layer.

Abstract: Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 ?m or less, preferably 5 nm or more and 0.1 ?m or less. The taper angle ? of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.

Abstract: Methods are disclosed herein for fabricating non-volatile memory devices. An exemplary method forms a heterostructure over a substrate. The heterostructure includes at least one semiconductor layer pair having a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer, the second semiconductor layer being different than the first semiconductor layer. A gate structure having a dummy gate is formed over a portion of the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and a channel region is defined between the source region and the drain region. During a gate replacement process, a nanocrystal floating gate is formed in the channel region from the second semiconductor layer. In some implementations, during the gate replacement process, a nanowire is also formed in the channel region from the first semiconductor layer.

Abstract: A metal coating method includes forming a metal layer on a substrate including a first member and a second member, the second member having a lower thermal conductivity than a thermal conductivity of the first member, and irradiating the metal layer formed on the first member and the second member with a laser beam such that, after irradiation, the metal layer formed on the first member remains, and the metal layer formed on the second member is removed.

Abstract: A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The channels extend in a direction crossing an upper surface of the substrate in the cell region. The gate stack includes a plurality of gate electrode layers spaced apart from each other on the substrate and enclosing the channels in the cell region. The pad separating region separates the gate stack into two or more regions in the pad region. The gate electrode layers have different lengths in the pad region.

Abstract: The invention relates to a manufacturing process of semiconductor material of element III nitride from a starting substrate, the process comprising: the formation of an intermediate layer based on silicon on a starting substrate, said intermediate layer comprising at least two adjacent zones of different crystalline orientations, especially a monocrystalline zone and an amorphous or poly-crystalline zone, growth via epitaxy of a layer of element III nitride on said intermediate layer, the intermediate layer being intended to be vaporised spontaneously during the step consisting of growing the layer of element III nitride via epitaxy.