Abstract: Magnetic random access memory (MRAM) packages with magnetic shield protections and methods of forming thereof are presented. Package contact traces are formed on the first major surface of the package substrate and package balls are formed on the second major surface of the package substrate. A die having active and inactive surfaces is provided on the first major surface of the package substrate. The die includes a magnetic storage element, such as an array of magnetic tunnel junctions (MTJs), formed in the die, die microbumps formed on the active surface. The package includes a top magnetic shield layer formed on the inactive surface of the die. The package may also include a first bottom magnetic shield in the form of magnetic shield traces disposed below the package contact traces. The package may further include a second bottom magnetic shield in the form of magnetic permeable underfill dielectric material.

Abstract: In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component.

Abstract: A field-effect transistor (a GaN-based HFET) includes a gate electrode, a gate electrode pad, a first wiring line connecting one end of the gate electrode and the gate electrode pad, a second wiring line connecting the other end of the gate electrode and the gate electrode pad, and a resistance element that is connected to the first wiring line and is capable of adjusting the impedance of the first wiring line.

Abstract: Disclosed herein is a light emitting device package and a light emitting device package module.

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Abstract: A two-side illuminated image sensor includes: a first optical sensor layer and a second optical sensor layer each including a plurality of optical sensing cells, and a signal wiring layer disposed between the first and second optical sensor layers. The first and second optical sensor layers may include a first color filter layer and a second color filter layer each including a plurality of color filters corresponding to the plurality of optical sensing cells.

Abstract: A magnetic tunnel junction device and a method to make the device are disclosed. The magnetic tunnel junction device comprises a first reference magnetic material layer, a tunnel barrier material layer, a free magnetic material layer between the first reference magnetic material layer and the tunnel barrier material layer, and a second reference magnetic material layer disposed on an opposite side of the tunnel barrier material layer from the free magnetic material layer, in which the second reference magnetic material layer is anti-magnetically exchanged coupled with the first reference magnetic material layer. A shift field Hshift experienced by the free magnetic material layer is substantially canceled by the anti-magnetic exchange coupling between the first reference magnetic material layer and the second reference magnetic material layer.

Abstract: Embodiments of the present disclosure are directed toward through-silicon via (TSV)-based devices and associated techniques and configurations. In one embodiment, an apparatus includes a die having active circuitry disposed on a first side of the die and a second side disposed opposite to the first side, a bulk semiconductor material disposed between the first side and the second side of the die and a device including one or more of a capacitor, resistor or resonator disposed in the bulk semiconductor material, the capacitor, resistor or resonator including one or more TSV structures that extend through the bulk semiconductor material, an electrically insulative material disposed in the one or more TSV structures and an electrode material or resistor material in contact with the electrically insulative material within the one or more TSV structures.

Abstract: Disclosed are a light-emitting device and a manufacturing method thereof. A light-emitting device according to a preferred embodiment of the disclosure comprises: a frame portion having a bottom and a sidewall; a light-emitting portion which is disposed on the frame portion and emits light; and a window portion disposed over the frame portion so as to cover the light-emitting portion.

Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.

Abstract: Methods of producing arrays of thin crystal grains of layered semiconductors, including the creation of stable atomic-layer-thick to micron-thick membranes of crystalline semiconductors by chemical vapor deposition.

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: The present invention generally relates to a MEMS device and a method of manufacture thereof. The RF electrode, and hence, the dielectric layer thereover, has a curved upper surface that substantially matches the contact area of the bottom surface of the movable plate. As such, the movable plate is able to have good contact with the dielectric layer and thus, good capacitance is achieved.

Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

Abstract: A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3C—SiC buffer layer on Si(001) comprising a porous buffer layer of 3C—SiC on a Si substrate wherein the porous buffer layer is produced through a solid state reaction.

Abstract: A semiconductor device is provided. The semiconductor device includes a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; a first conductive type first well region disposed in the second conductive type body region; a gate structure disposed over the top surface of the first conductive type substrate; a source region, wherein the source region includes a heavily-doped first conductive type source region and is disposed in the second conductive type body region; and a drain region, wherein the drain region is heavily doped first conductive type and is disposed in the first conductive type first well region.

Abstract: An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.

Abstract: In a method of manufacturing an optical sheet, a stacked structure may be formed by alternatively and repeatedly stacking at least one transparent layer and at least one light scattering layer. A first cut face may be formed by partially cutting the stacked structure. A second cut face may be formed by partially cutting the stacked structure. The second cut face may be parallel to the first cut face.

Abstract: The instant invention provides a pixel structure. The pixel structure includes a substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, a plurality of metallic optical structures, a pixel electrode, and a common electrode. The gate electrode is disposed on the substrate. The gate insulating layer is on the gate electrode. The source electrode and the drain electrode are disposed on the gate insulating layer. The plurality of metallic optical structures are embedded in the gate insulating layer. The pixel electrode electrically connects the drain electrode and is disposed on the plurality of metallic optical structures. The common electrode is disposed under the plurality of metallic optical structures.