Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: A light-emitting device includes: a light-emitting element; a coating member that covers the light-emitting element; and two external connection electrodes exposed form a first surface of the coating member. Each of the external connection electrodes includes an electrode buried in the coating member; and a metal layer formed on the electrode. A surface of each of the metal layers is exposed from the first surface of the coating member. The first surface of the coating member includes a plurality of grooves between the external connection electrodes.

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Abstract: A compound semiconductor device includes: a first layer of nitride semiconductor, the first layer being doped with Fe; a channel layer of nitride semiconductor above the first layer; and a barrier layer of nitride semiconductor above the channel layer, wherein the channel layer includes: a two-dimensional electron gas region in which the two-dimensional electron gas exists; and an Al-containing region between the two-dimensional electron gas region and the first layer, an Al concentration in the Al-containing region being 5×1017 atoms/cm3 or more and less than 1×1019 atoms/cm3.

Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap.

Abstract: Sensor packages and methods of assembling a sensor in a sensor package are provided. A preferred embodiment comprises: a base including a sensor coupled to the base wherein the base has at least one electrical connection location and a first mechanical mating interface in the shape of an arc; an electronics package with at least one electrical connection location; and a ring coupled between the base and the electronics package wherein the ring electrically connects the at least one electrical connection location on the base and the at least one electrical connection location on the electronics package and wherein the base has a second mechanical mating interface in the shape of an arc that is reciprocal to the first mating interface.

Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.

Abstract: A magnetic memory device and a method to make the device is disclosed. The magnetic memory device comprises a free magnetic layer that includes a hard magnetic material layer, a soft magnetic material layer and a coupling layer that is between the hard magnetic material layer and the soft magnetic material layer. The coupling layer comprises a magnetic material that has oxidized edges. In one embodiment, the magnetic material of the coupling layer comprises a Heusler alloy or a silicon-based magnetic material. A predetermined amount of the coupling layer is oxidized to controllably reduce the switching current Jc0 of the free magnetic layer to be about half of the switching current if the coupling layer comprised substantially all magnetic material and no oxide.

Abstract: Disclosed herein is a light emitting device package and a light emitting device package module.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: A light-emitting diode package includes a frame portion with a chip-mounting region defined in an upper portion thereof, and first and second frames spaced apart from each other. A light-emitting diode is mounted on at least a portion of the chip-mounting region with a bonding layer interposed therebetween. The frame portion includes a depressed portion formed on an upper surface thereof, and the depressed portion includes the chip-mounting region defined on a bottom thereof. The depressed portion also includes a step portion disposed at an outer upper end thereof.

Abstract: At least one method, apparatus and system disclosed involves a semiconductor substrate on which NMOS and PMOS devices with enhanced current drives may be formed. A first substrate having an enhanced electron mobility is formed. A second substrate having an enhanced hole mobility is formed. The first substrate and the second substrate are bonded for forming a third substrate. A first channel on the third substrate characterized by the enhanced electron mobility is formed. A second channel on the third substrate characterized by the enhanced hole mobility is formed.

Abstract: A field effect transistor (FET) includes a gate dielectric layer, a two-dimensional (2D) channel layer formed on the gate dielectric layer and a gate electrode. The 2D channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET. The 2D channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region. A source electrode covers the first finger regions, and a drain electrode covers the second finger regions.

Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

Abstract: Provided is a light emitting semiconductor device comprising a flexible dielectric layer, a conductive layer on at least one side of the dielectric layer, at least one cavity or via in the dielectric substrate, and a light emitting semiconductor supported by the cavity or via. Also provided is a support article comprising a flexible dielectric layer, a conductive layer on at least one side and at least one cavity or via in the dielectric substrate. Further provided is a flexible light emitting semiconductor device system comprising the above-described light emitting semiconductor device attached to the above-described support article.