Abstract: A MEMS switch includes a first signal line provided in a first beam, a first GND adjacent to the first signal line, a second signal line provided in a second beam, and a second GND adjacent to the second signal line. A contact terminal is fixed to any one of the first signal line and the second signal line and performs connection between the first signal line and the second signal line according to deformation of the first beam.

Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

Abstract: The present disclosure provides a method for forming an electrostatic discharge (ESD) protection device, including: providing a substrate including an input region; forming a plurality of fins on the substrate in the input region; forming a well region, doped with first-type ions, in the plurality of fins and in the substrate; and forming an epitaxial layer on each fin in the input region. The method further includes: forming a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer; forming an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and forming a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions.

Abstract: To achieve high processing capability, a semiconductor device includes first and second circuits, first to third wirings, and first to fourth transistors. The first circuit is electrically connected to the first wiring and a gate of the first transistor. One of a source and a drain of the first transistor is electrically connected to the second wiring. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. The second circuit is electrically connected to the first wiring and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to the third wiring. The other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor. One of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor.

Abstract: The invention relates to a manufacturing process of semiconductor material of element III nitride from a starting substrate, the process comprising: the formation of an intermediate layer based on silicon on a starting substrate, said intermediate layer comprising at least two adjacent zones of different crystalline orientations, especially a monocrystalline zone and an amorphous or poly-crystalline zone, growth via epitaxy of a layer of element III nitride on said intermediate layer, the intermediate layer being intended to be vaporised spontaneously during the step consisting of growing the layer of element III nitride via epitaxy.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: A manufacturing method of an LED package structure includes the steps as follows: providing an LED package structure assembly, which has a substrate layer, an LED chip set located on the substrate layer, and an encapsulating gel layer covering the LED chip set; taking a first blade to saw the LED package structure assembly from the encapsulating gel layer to the substrate layer until a plurality of sawing grooves are formed on the substrate layer; and taking a second blade to saw the LED package structure assembly along each sawing groove until the second blade passes through the substrate layer, thereby forming a plurality of LED package structures separated from each other. Wherein a hardness of the first blade is greater than that of the second blade, and a thickness of the second blade is less than that of the first blade.

Abstract: An image sensor includes a first color separation element configured to separate an incident light, the incident light being separated into a mixture of a first color light and a third color light, and separated into a second color light; and a sensor array unit including a plurality of pixels configured to sense the separated incident light, the sensor array including a first pixel region and a second pixel region that are alternately arranged in a first direction and a second direction, the second direction crossing the first direction, wherein a stack of a first light sensing layer configured to sense the first color light and a third light sensing layer configured to sense the third color light is provided in the first pixel region, and a second light sensing layer configured to sense the second color light is provided in the second pixel region.

Abstract: Magnetic random access memory (MRAM) fan-out wafer level packages with package level and chip level magnetic shielding and methods of forming these magnetic shields processed at the wafer-level are disclosed. The method includes providing a MRAM wafer prepared with a plurality of MRAM dies. The MRAM wafer is processed to form a magnetic shield layer over the front side of the MRAM wafer, and the wafer is separated into a plurality of individual dies. An individual MRAM die includes front, back and lateral surfaces and the magnetic shield layer is disposed over the front surface of the MRAM die. Magnetic shield structures are provided over the individual MRAM dies. The magnetic shield structure encapsulates and surrounds back and lateral surfaces of the MRAM die. An encapsulation layer is formed to cover the individual MRAM dies which are provided with magnetic shield structures.

Abstract: In a method of manufacturing an optical sheet, a stacked structure may be formed by alternatively and repeatedly stacking at least one transparent layer and at least one light scattering layer. A first cut face may be formed by partially cutting the stacked structure. A second cut face may be formed by partially cutting the stacked structure. The second cut face may be parallel to the first cut face.

Abstract: A panel to detect X-rays includes a plurality of signal lines, a plurality of gate lines, and a plurality of cells in areas adjacent intersections of respective ones of the gate and control lines. A first area includes a first cell having a driving circuit, and a second area includes a second cell which omits a driving circuit. Data lines connected to respective ones of the cells carry signals from which an X-ray image is generated. The second cell may be located in a dummy cell area of the panel.

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.

Abstract: The present disclosure generally relates to the fabrication of metal-oxide-semiconductor (MOS) select transistors in a vertical orientation such that the transistor pair fits within the footprint of a 4F2 memory cell. The present disclosure further relates to the simultaneous fabrication of a vertical stack of transistors in which each transistor is distinct, as opposed to being serially connected in a NAND-like string. An initial stack of materials is built to include silicon layers to act as source and drain regions as well as to serve as epitaxial growth seed points. As such, the transistor disclosed may be utilized in conjunction with memory elements such as Phase Change, Resistive, or Magnetic RAM memory within array designs, among others.

Abstract: A display may have an array of pixels with light-emitting diodes that emit light to form images. The display may have a substrate with thin-film transistor circuitry for supplying signals to the light-emitting diodes. Anodes may be formed on the thin-film transistor circuitry, emissive material may be formed on the anodes, and a cathode layer may overlap the anodes. During operation, currents may flow between the anodes and the cathode layer to illuminate the diodes. An array of electrical components such as an array of light sensors in an integrated circuit may be mounted under the substrate. An array of corresponding light transmitting windows may be formed in the display each of which may allow light to pass through the display to a corresponding one of the light sensors. Light transmitting windows may be formed by patterning the cathode layer and supplying the windows with antireflection layers.

Abstract: Provided is a semiconductor device including an active region defined by a separation region on a main surface of a semiconductor substrate, and a field effect transistor formed in the active region. A boundary portion, over which a gate electrode pattern strides, is disposed in a boundary between the active region and the separation region and is configured such that a length of one side, in a direction of a gate length of the field effect transistor formed in the active region, becomes larger than the gate length and does not come into contact with at least one of a pair of source and drain regions of the field effect transistor.

Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

Abstract: A current sensor integrated circuit includes a lead frame having a primary conductor and at least one secondary lead, a semiconductor die disposed adjacent to the primary conductor, an insulation structure disposed between the primary conductor and the semiconductor die, and a non-conductive insulative material enclosing the semiconductor die, the insulation structure, a first portion of the primary conductor, and a first portion of the at least one secondary lead to form a package. The first portion of the at least one secondary lead (between a first end proximal to the primary conductor and a second end proximal to the second, exposed portion of the at least one secondary lead) has a thickness that is less than a thickness of the second, exposed portion of the least one secondary lead. A distance between the second, exposed portion of the primary conductor and the second, exposed portion of the at least one secondary lead is at least 7.2 mm.

Abstract: A device includes a vertical semiconductor switch including (i) a gate terminal and a first terminal provided on a substrate and (ii) a second terminal provided on the substrate, where the vertical semiconductor switch is configured to electrically connect or disconnect the first terminal and the second terminal, a first insulative film provided on the substrate, a second insulative film provided on the substrate, where the second insulative film is in contact with the first insulative film and thinner than the first insulative film, and a zener diode formed on the first insulative film and the second insulative film, where the zener diode includes a first portion that is formed on the first insulative film and connected to the first surface of the substrate and a second portion that is formed on the second insulative film and connected to the gate terminal.

Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.