Patents Examined by Selim Ahmed
  • Methods of fabricating semiconductor devices including complementary metal oxide semiconductor transistors
    Patent number: 9899272
    Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Poren Tang, Sunjung Steve Kim, Moon Seung Yang, Seung Hun Lee, Hyun Jung Lee, Geun Hee Jeong
  • Method of manufacturing semiconductor substrate including separating two semiconductor layers from a growth substrate
    Patent number: 9899565
    Abstract: A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Jo Tak, Sam Mook Kang, Mi Hyun Kim, Jun Youn Kim, Young Soo Park, Misaichi Takeuchi
  • Uniform gate length in vertical field effect transistors
    Patent number: 9893181
    Abstract: A method of fabricating a vertical field effect transistor includes forming a base layer on a doped layer that is formed on a substrate, and forming fin hard masks above the base layer. Spacers are formed adjacent to each side of each of the fin hard masks above the base layer. A width dimension of each of the spacers is the same. Gaps between the spacers are filled with oxide prior to removing the spacers. The spacers are removed to leave gaps of the same width on each side of each of the fin hard masks. An etch in the gaps forms a plurality of fins below the fin hard masks. A height dimension of each of the plurality of fins is the same and a space between two of the plurality of fins is different than a second space between two others of the plurality of fins.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Deposition methods for uniform and conformal hybrid titanium oxide films
    Patent number: 9881787
    Abstract: Methods for depositing titanium oxide films by atomic layer deposition are disclosed. Titanium oxide films may include a titanium nitride cap, an oxygen rich titanium nitride cap or a mixed oxide nitride layer. Also described are methods for self-aligned double patterning including titanium oxide spacer films.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 30, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Teh Kao, Benjamin Schmiege, Xuesong Lu, Juno Yu-Ting Huang, Yu Lei, Yung-Hsin Lee, Srinivas Gandikota, Rajkumar Jakkaraju, Chikuang Charles Wang, Ghazal Saheli, Benjamin C. Wang, Xinliang Lu, Pingyan Lei
  • Semiconductor device assemblies including intermetallic compound interconnect structures
    Patent number: 9881886
    Abstract: A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Jaspreet S. Gandhi
  • Method for fabricating semiconductor device
    Patent number: 9875941
    Abstract: A method for fabricating semiconductor device is disclosed. First, a first fin-shaped structure and a second fin-shaped structure are formed on a substrate, and a shallow trench isolation (STI) is formed around the first fin-shaped structure and the second fin-shaped structure, a patterned hard mask is formed on the STI. Next, part of the first fin-shaped structure and part of the second fin-shaped structure adjacent to two sides of the patterned hard mask are removed for forming a first recess and a second recess, and a dielectric material is formed into the first recess and the second recess.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang
  • Deposition of metal dielectric film for hardmasks
    Patent number: 9875890
    Abstract: A system and method for depositing a metal dielectric film includes arranging a substrate in a plasma enhanced chemical vapor deposition (PECVD) processing chamber; supplying a carrier gas to the PECVD processing chamber; supplying a dielectric precursor gas to the PECVD processing chamber; supplying a metal precursor gas to the PECVD processing chamber; creating plasma in the PECVD processing chamber; and depositing a metal dielectric film on the substrate at a process temperature that is less than 500° C.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 23, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Fayaz Shaikh, Sirish Reddy
  • Mask assembly, apparatus, and method of manufacturing display device using the mask assembly
    Patent number: 9876170
    Abstract: Provided is a mask assembly, an apparatus, and a method of manufacturing a display apparatus using such mask assembly and apparatus. The mask assembly deposits a deposition material on a first pixel among a plurality of pixels disposed on a device substrate and including the first pixel and a second pixel includes a mask substrate, a molding layer stacked on the mask substrate and including a hole corresponding to a position of the second pixel, a blocking plate detachably mounted in the hole and configured to block the second pixel from the deposition material by covering the second pixel when the blocking plate is detached from the hole.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 23, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngsuk Cho, Taemin Kang, Jaesik Kim, Jeongkuk Kim
  • Production process for device
    Patent number: 9868633
    Abstract: A production process for a device in which a first substrate and a second substrate are bonded to each other with bonding surfaces thereof mutually bonded and the second substrate has a through-hole, the production process including the steps of bonding the first substrate and the second substrate to each other with the presence of a non-bonding region formed by a recessed shape portion recessed from at least one of the bonding surface of the first substrate and the bonding surface of the second substrate; and causing at least a part of a portion of the second substrate corresponding to the non-bonding region to pass through.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 16, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazunori Kikuchi
  • Method for manufacturing isolation structure
    Patent number: 9865496
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 9, 2018
    Assignee: SK Hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Plasma generator, annealing device, deposition crystallization apparatus and annealing process
    Patent number: 9865435
    Abstract: A plasma generator, a plasma annealing device, a deposition crystallization apparatus and a plasma annealing process are disclosed. The plasma generator includes: a gas chamber; a gas intake member configured to introduce a gas into the gas chamber; a cathode and an anode that are configured to apply an electric field to the gas introduced into the gas chamber to ionize the gas into plasma; a cooling water circulation member configured to control a temperature of the plasma generator; and a plasma beam outlet disposed on a top face of the gas chamber. The plasma annealing device including the plasma generator can generate a plasma beam, which can be used in annealing to amorphous silicon and crystallize the amorphous silicon to polycrystalline silicon.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: January 9, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangjun Tian, Seiji Fujino
  • Methods for manufacturing a semiconductor device
    Patent number: 9859163
    Abstract: A method for manufacturing a semiconductor device includes forming gate structures spaced apart from each other on a substrate, gate spacers covering sidewalls of the gate structures, and an interlayer insulating layer covering the gate spacers, forming a contact hole that penetrates the interlayer insulating layer to expose a sidewall of at least one of the gate spacers, forming a sacrificial gap-fill pattern filling a lower portion of the contact hole, forming a contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern, and forming a contact filling the contact hole after removing the sacrificial gap-fill pattern.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyounghoon Han, Junho Yoon, Kisoo Chang
  • Process for fabricating silicon nanostructures
    Patent number: 9859366
    Abstract: A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: January 2, 2018
    Assignee: Advanced Silicon Group, Inc.
    Inventors: Brent A. Buchine, Marcie R. Black, Faris Modawar
  • Solution-processed sol-gel films including a crystallization aid, devices including same, and methods
    Patent number: 9859116
    Abstract: A method for preparing a sol-gel film is disclosed. The method comprises providing a sol-gel composition comprising one or more sol-gel film precursors and a crystallization aid, and processing the sol-gel composition by solution processing to form the sol-gel film. In certain embodiments, the sol-gel film comprises one or more metal oxides. A preferred crystallization aid includes triphenylphosphine oxide. A composition for making a sol-gel film, a sol-gel film, a device including a sol-gel film and a method for making such device are also disclosed.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yuhua Niu, Peter T. Kazlas
  • CMOS-based thermopile with reduced thermal conductance
    Patent number: 9853086
    Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: December 26, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Toan Tran, Jeffrey R. Debord, Ashesh Parikh, Bradley David Sucher
  • Self aligned conductive lines
    Patent number: 9852946
    Abstract: A method for forming conductive lines on a wafer comprises forming a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to the first and second sacrificial mandrels. A filler material is deposited on the second hardmask. A first mask is formed on a portion of the second sacrificial mandrel. A first cavity and a second cavity are formed that expose portions of the second hardmask, and exposed portions of the second mask and exposed portions of the filler material are removed to expose portions of the first hardmask. Exposed portions of the first hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. Exposed portions of the insulator layer are removed to form a trench in the insulator layer and the trench is filled with a conductive material.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole Saulnier
  • Method of manufacturing a semiconductor device having a trench at least partially filled with a conductive material in a semiconductor substrate
    Patent number: 9842904
    Abstract: A method of manufacturing a semiconductor device includes forming a first trench in a semiconductor substrate from a first side, forming a semiconductor layer adjoining the semiconductor substrate at the first side, the semiconductor layer capping the first trench at the first side, and forming a contact at a second side of the semiconductor substrate opposite to the first side.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: December 12, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Reinhard Ploss, Hans-Joachim Schulze
  • Laterally diffused metal oxide semiconductor device and manufacturing method therefor
    Patent number: 9837532
    Abstract: A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: December 5, 2017
    Assignee: CSMC Technologies Fab1 Co., Ltd.
    Inventors: Guangsheng Zhang, Sen Zhang
  • Forming strained and unstrained features on a substrate
    Patent number: 9837408
    Abstract: Embodiments are directed to a method of forming features of a semiconductor device. The method includes forming a first feature including a first type of semiconductor material, which can be tensile or can have compressive strain. The method further includes forming an enclosure structure including a second type of semiconductor material, wherein the first feature includes first feature sidewall surfaces extending around a circumference of the first feature. The enclosure structure is adjacent at least a portion of the first feature sidewall surfaces and extends around the circumference of the first feature.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Zheng Xu
  • Image sensor and method for fabricating the same
    Patent number: 9825075
    Abstract: A method for fabricating an image sensor in accordance with an embodiment of the inventive concepts may include forming first and second photodiodes within a substrate, forming first and second gate electrodes over the substrate, the first gate electrode vertically partially overlapping the first photodiode and the second gate electrode vertically partially overlapping the second photodiode, forming an impurity injection region comprising first and second type impurities between the first and the second gate electrodes, and performing an annealing process to form a floating diffusion region comprising the first type impurities and a channel region comprising the second type impurities. The channel region surrounds lateral surfaces and a bottom surface of the floating diffusion region.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Sung-Kun Park