Abstract: A method for fabricating a substrate includes forming a first substrate including a thin film transistor array, and inspecting a first surface of an inspecting device, wherein inspecting the first surface of the inspection device includes: generating first measurement data by detecting a first measurement light that is parallel to a surface of an inspection region in the first surface, generating second measurement data by detecting a second measurement light that is parallel to the surface of the inspection region, and inspecting a state of a surface of the inspection region by comparing the first measurement data with the second measurement data.

Abstract: A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.

Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

Abstract: A method for producing a semiconductor light-emitting device containing a substrate, an element and an encapsulating material as constituent members is provided. The method involves providing the substrate with the element; potting at least one encapsulating material (i) before curing selected from addition polymerization-type encapsulating materials and polycondensation-type encapsulating materials onto the substrate to cover the element; curing the potted encapsulating material (i); potting a polycondensation-type encapsulating material (ii) before curing onto the encapsulating material (i) after curing which covers the element, and then curing the potted polycondensation-type encapsulating material (ii), thereby laminating the encapsulating material. A semiconductor light-emitting device produced by the method is also provided, in which two or more layers each containing the encapsulating material are laminated.

Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.

Abstract: A method of fabricating high-k/metal gate semiconductor device by incorporating an enhanced annealing process is provided. The enhanced annealing process in accordance with the disclosure can be operated at relatively low temperature and high pressure and thus can improve the k value and repair the above-mentioned deficiencies of the HK layer. Under the enhanced annealing process in accordance with the disclosure, H+ can be diffused from the ammonia gas and to repair the broken bonds because of high pressure, while avoiding adversely impact the NiSi and implanted ions in the HK layer due to the low temperature. The enhanced annealing process in accordance with the disclosure can be performed between 300° C. to 500° C. at a pressure of 15-20 atm for 15 to 50 minutes in some embodiments.

Abstract: A semiconductor device includes a semiconductor body and a rear side insertion structure. The semiconductor body has a first surface at a front side and a second surface parallel to the first surface at a rear side, an active area and an edge termination area separating the active area from an outer surface of the semiconductor body. The outer surface connects the first and second surfaces, and element structures in the active area are predominantly formed closer to the first surface than to the second surface. The rear side insertion structure extends from the second surface into the semiconductor body in the edge termination area.

Abstract: A light emitting device includes a substrate, a light emitting element provided on the substrate, a first resin layer provided on the substrate to directly cover the light emitting element having a first side surface and a second side surface, and the first side surface and the second side surface differ from each other in inclination angle with respect to the substrate, and a second resin layer provided so as to surround side surfaces of the first resin layer.

Abstract: A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

Abstract: A cobalt deposition process, including: volatilizing a cobalt precursor selected from among CCTBA, CCTMSA, and CCBTMSA, to form a precursor vapor; and contacting the precursor vapor with a substrate under vapor deposition conditions effective for depositing on the substrate (i) high purity, low resistivity cobalt or (ii) cobalt that is annealable by thermal annealing to form high purity, low resistivity cobalt. Such cobalt deposition process can be used to manufacture product articles in which the deposited cobalt forms an electrode, capping layer, encapsulating layer, diffusion layer, or seed for electroplating of metal thereon, e.g., a semiconductor device, flat-panel display, or solar panel.

Abstract: A process for forming an integrated circuit with a dilution doped resistor with a resistance that may be tuned by partially blocking the implant used to dope the resistor. A process for forming an integrated circuit with a dilution doped polysilicon resistor by partially blocking the resistor dopant implant from a portion of the polysilicon resistor body.

Abstract: A configuration of a display device capable of color display is obtained. The display device includes a plurality of rod-shaped light-emitting elements each of which includes a semiconductor and which emit light beams having wavelength distributions different from each other, and alignment electrodes (12). The alignment electrodes (12) include a first electrode pair (12a), a second electrode pair (12b), and a third electrode pair (12c).

Abstract: Systems and methods are provided that enable the production of semiconductor devices having a metal nitride layer in direct contact with a semiconductor layer to form a Schottky diode, such as a TiN gate on an AlGaN/GaN high electron mobility transistor (HEMT). Metal nitrides offer exceptional thermal stability and a lower diffusion coefficient. Technology enabled by embodiments of the present disclosure improves the reliability of GaN-based microwave power transistors.

Abstract: This method for estimating the depth of latent scratches in SiC substrates includes an etching step, a measurement step, and an estimation step. In the etching step, a SiC substrate in which at least the surface is formed from single crystal SiC, and which has been subjected to machining, is subjected to heat treatment under Si atmosphere to etch the surface of the SiC substrate. In the measurement step, the surface roughness or the residual stress of the SiC substrate which has been subjected to the etching step is measured. In the estimation step, the depth of latent scratches or the presence or absence of latent scratches in the SiC substrate before the etching step are estimated on the basis of the results obtained in the measurement step.

Abstract: An array substrate includes a gate electrode and a source electrode arranged on a base substrate of the array substrate. The source electrode has a first end connected to a pixel electrode on the array substrate, and a second end opposite to the first end. A tip of the second end is provided with an extension portion, and an orthogonal projection of the extension portion onto the base substrate extends beyond an orthogonal projection of the gate electrode onto the base substrate.

Abstract: A method for equalizing the thickness variation of a substrate stack which is comprised of a product substrate and a carrier substrate and which is connected in particular by means of an interconnect layer, by local application of local thickness peaks by means of an application apparatus which has at least one application unit. Furthermore this invention relates to a corresponding device.

Abstract: A quantum dot light emitting device includes a base plate and an anode, a hole transportation layer, a light emissive layer, an electron transportation layer, and a cathode arranged on the same side of the base plate. The anode and the cathode are opposite to and spaced from each other and receive the hole transportation layer, the light emissive layer, and the electron transportation layer to be interposed therebetween. The hole transportation layer is connected to the anode. The light emissive layer and the electron transportation layer are sequentially stacked on the hole transportation layer that is distant from the anode. The electron transportation layer is connected to the cathode. The light emissive layer includes a quantum dot light emitting material and a small-molecule organic light emitting material, which is filled in gaps present in the quantum dot light emitting material.

Abstract: Embodiments of systems and methods for substrate thermal processing using a hot plate with a programmable array of lift devices for multi-bake process optimization are presented. In an embodiment, an apparatus includes a base with an upper surface configured to receive the substrate. The base may include at least one heater for heating the substrate while on or in the vicinity of the base, and a plurality of lift devices configured to selectively extend from the upper surface of the base to support the substrate above the base when extended, and allow the substrate to rest on the upper surface of the base when retracted, each lift device being actuated independently of the other lift devices by an actuating mechanism. Additionally, the apparatus may include a controller for controlling the plurality of actuating mechanisms.

Abstract: A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.

Abstract: Provided is a method of manufacturing a mask including preparing a support plate, forming a light blocking layer on the support plate, curing a predetermined region of the light blocking layer, and removing other region of the light blocking layer, excluding the predetermined region.