Abstract: Provided is a method of manufacturing a mask including preparing a support plate, forming a light blocking layer on the support plate, curing a predetermined region of the light blocking layer, and removing other region of the light blocking layer, excluding the predetermined region.

Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

Abstract: Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer and the resulting device are provided. Embodiments include providing a SOI structure having a substrate, BOX, device and metallization layers; bonding a handling layer to the metallization layer; removing the substrate; forming a passivation oxide layer over the BOX; forming first and second trenches through the passivation, BOX, and device layers down to the metallization layer; forming a third trench through the passivation layer and a portion of the BOX above a PA power cell region of the SOI structure, a thin portion of the BOX remaining; forming a first backside contact in the first trench; and forming a second backside contact in the second and third trenches and over a portion of the passivation oxide layer.

Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).

Abstract: Provided herein are methods of forming thin films. In some embodiments, to form a thin film, a precursor adsorption layer including an organic ligand is formed by supplying a precursor including a metal or silicon central atom, and the organic ligand onto a lower structure. An intermediate result layer is formed by supplying a non-oxidant onto the precursor adsorption layer. In forming the intermediate result layer, the organic ligand included in the precursor adsorption layer is substituted with a substituent. An oxide film including the central atom is formed from the intermediate result layer by supplying an oxidant onto the intermediate result layer.

Abstract: A method of forming an interconnect structure is provided. The method includes forming a first dielectric layer, and forming an opening in the first dielectric layer. The method also includes applying a gas to the first dielectric layer adjacent to the opening, where after applying the gas to the first dielectric layer adjacent to the opening, a bottom surface of the opening has been planarized. The method also includes etching the first dielectric layer through the opening to expose a first contact underlying the first dielectric layer, and forming a conductive line in the opening.

Abstract: A transfer apparatus includes a supporting member, a free electron excitation device and a detection device; the free electrons excitation device is configured to excite semiconductor material of an object to be transferred to generate free electrons, and the detection device is configured to detect whether material of a surface of the transferred object in contact with the support surface of the supporting member is conductive under excitation by the free electron excitation device. A laser annealing apparatus comprising the transfer apparatus is further provided.

Abstract: An electro-optical device is capable of high quality images. An electro-optical device (200) includes a first capacitive element (491), a second capacitive element (492), and a third capacitive element (493). The first capacitive element (491) includes a first conductive film (408), a first part of a second conductive film (411), and a first dielectric film (410). The second capacitive element (492) includes a third conductive film (416), a second part of a fourth conductive film (418), and a second dielectric film (417). The third capacitive element (493) includes the third conductive film (416), a third part of the fourth conductive film (418), and the second dielectric film (417). Since a capacitive element that includes a large capacitance value is formed in a narrow region, even if the pixel becomes smaller as the definition is increased, it is possible to realize an excellent electro-optical device in which display defects are suppressed.

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.

Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming an interlayer insulating layer that comprises a first region and a second region, forming an etch stop pattern for exposing the second region in the first region of the interlayer insulating layer and forming a mask pattern that comprises a first via-hole that exposes an upper surface of the etch stop pattern and a second via-hole that penetrates the interlayer insulating layer on the interlayer insulating layer and the etch stop pattern.

Abstract: Embodiments of the disclosure disclose an electroluminescence display device and a fabrication method thereof. The device comprises a color filter substrate. The color filter substrate comprises: a first substrate, and a first electrode, an organic electroluminescence layer and a second electrode sequentially provided on the first substrate. The color filter substrate further comprises: a first protective layer, provided on the second electrode and covering the second electrode and the organic electroluminescence layer below the second electrode; and a first connection electrode, provided on the first protective layer and connected to the second electrode.

Abstract: A solar cell is provided. The solar cell includes a silicon substrate, a back electrode, a doped silicon layer, and an upper electrode. The silicon substrate includes a first surface, a second surface, and a number of three-dimensional nano-structures located on the first surface. The three-dimensional nano-structures are located on the second surface. The three-dimensional nano-structures are linear protruding structures that are spaced from each other, and a cross section of each linear protruding structure is an arc. The doped silicon layer is attached to the three-dimensional nano-structures and the second surface between the three-dimensional nano-structures.

Abstract: An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

Abstract: A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive connecting element disposed on the substrate. The conductive connecting element comprises a connecting part and an extending part. The connecting part has a bottom portion electrically contacting with the conductive layer. The extending part laterally extends outwards from a top portion of the connecting part, and the extending part and the connecting part are respectively formed of different materials.

Abstract: Methods of hydrogenation of passivated contacts using materials having hydrogen impurities are provided. An example method includes applying, to a passivated contact, a layer of a material, the material containing hydrogen impurities. The method further includes subsequently annealing the material and subsequently removing the material from the passivated contact.

Abstract: A method for manufacturing a silicon carbide semiconductor device comprises: a step for forming a front-surface electrode (30) on a front surface side of a silicon carbide wafer (10); a step for thinning the silicon carbide wafer (10) by reducing a thickness of the silicon carbide wafer (10) from a back surface side thereof; a step for providing a metal layer (21) on the back surface of the thinned silicon carbide wafer (10); a step for irradiating the metal layer (21) with laser light, while applying an external force such that the silicon carbide wafer and the metal layer are planarized, to form the carbide layer (20) obtained by a reaction with carbon in the silicon carbide wafer (10), on a back surface side of the metal layer (21); and a step for forming a back-surface electrode (40) on a back surface side of the carbide layer (20).

Abstract: A method of forming a micromechanical structure comprising, forming a sacrificial layer on a surface and walls of a trench in a substrate; depositing a structural layer over the sacrificial layer, extending into the trench, selectively etching the structural layer to define a pattern having a boundary, at least a portion of the structural layer overlying a respective portion of the trench being removed and at least a portion of the structural layer extending into the trench being preserved at the boundary; and removing at least a portion of the sacrificial layer from underneath the structural layer, prior to removal of at least a portion of the sacrificial layer extending into the trench at the structural boundary. A micromechanical structure formed by the method is also provided.

Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.