Patents Examined by Shamim Ahmed
  • Patent number: 10968523
    Abstract: A method to partially decrease a reflectivity of a region on a mirror platform includes isolating the region on a surface of the mirror platform and removing a first material from the surface of the mirror platform within the region. The reflectivity of the mirror platform is decreased within the region.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 6, 2021
    Assignee: ELECTRIC MIRROR, LLC
    Inventors: James V. Mischel, Jr., James V. Mischel, Sr.
  • Patent number: 10971363
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
  • Patent number: 10971357
    Abstract: A method of modifying a layer in a semiconductor device is provided. The method includes depositing a low quality film on a semiconductor substrate, and exposing a surface of the low quality film to a first process gas comprising helium while the substrate is heated to a first temperature, and exposing a surface of the low quality film to a second process gas comprising oxygen gas while the substrate is heated to a second temperature that is different than the first temperature. The electrical properties of the film are improved by undergoing the aforementioned processes.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: April 6, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Wei Liu, Theresa Kramer Guarini, Linlin Wang, Malcolm Bevan, Johanes S. Swenberg, Vladimir Nagorny, Bernard L. Hwang, Kin Pong Lo, Lara Hawrylchak, Rene George
  • Patent number: 10971353
    Abstract: The present disclosure provides a method for dehydrating a semiconductor structure, including providing a semiconductive substrate, forming a trench on the semiconductive substrate, dispensing an agent in liquid form into the trench, solidifying the agent, and dehydrating a surface in the trench by transforming the agent from solid form to vapor form.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Chieh Lee
  • Patent number: 10964513
    Abstract: Provided is a plasma processing apparatus including a processing chamber which is disposed in a vacuum vessel and able to be decompressed, a sample stage on a top surface of which a wafer to be processed is mounted, an opening which is configured to supply a heat-transfer gas to a gap between the wafer and the top surface of the sample stage, a regulator which regulates a flow rate of the heat-transfer gas, and a controller which regulates an operation of the regulator based on a pressure of the gap detected using an amount of the heat-transfer gas leaking from the regulator to the processing chamber through the gap while the wafer is mounted on the sample stage and an amount of the heat-transfer gas supplied from the opening to the processing chamber while the wafer is not mounted on the sample stage.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 30, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Shintarou Nakatani, Tsunehiko Tsubone
  • Patent number: 10961400
    Abstract: The present invention provides the following method for forming a multilayer coating film. The method comprises forming an uncured coating film of a specific primer paint composition (A) on a substrate, forming a top coating film of a specific top paint composition (B) on the uncured coating film, and simultaneously drying the films. The primer paint composition (A) is a paint composition comprising an epoxy resin (a1), a rust preventive pigment (a2), a color pigment (a3), and an extender pigment (a4); and the top paint composition (B) is a paint composition comprising an acrylic resin (b1) and an active methylene blocked polyisocyanate compound (b2).
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 30, 2021
    Assignee: KANSAI PAINT CO., LTD.
    Inventors: Keitaro Yamamoto, Masahiro Tada, Hirohisa Tsuda, Hideaki Katsuta
  • Patent number: 10961487
    Abstract: A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pinlei Edmund Chu, Chun-Wei Hsu, Ling-Fu Nieh, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Patent number: 10953514
    Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
  • Patent number: 10957593
    Abstract: A method of processing a wafer includes a grinding step of grinding a wafer that has first insulating films covering via electrodes, from a reverse side thereof, an electrode protruding step of protruding the via electrodes covered with the first insulating films from the reverse side by way of etching, a distorted layer forming step of forming a distorted layer on the reverse side of the wafer, an insulating film forming step of forming a second insulating film on the reverse side of the wafer, and an electrode forming step of removing the first insulating films and the second insulating film from the regions where they overlap the via electrodes, and forming reverse-side electrodes connected to the via electrodes.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 23, 2021
    Assignee: DISCO CORPORATION
    Inventors: Yoshiteru Nishida, Hidekazu Iida, Kenta Chito, Youngsuk Kim
  • Patent number: 10957542
    Abstract: A method of processing a wafer includes a grinding step of grinding a reverse side of a wafer that has first insulating films covering via electrodes, an electrode protruding step of protruding the via electrodes covered with the first insulating films from the reverse side by supplying a first etching gas turned to a plasma, an insulating film forming step of covering the reverse side with a second insulating film, a via electrode exposing step of supplying a second etching gas turned to a plasma to expose the via electrodes after having formed a resist film having openings overlapping the via electrodes, and an electrode forming step of forming electrodes connected to the via electrodes.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 23, 2021
    Assignee: DISCO CORPORATION
    Inventor: Youngsuk Kim
  • Patent number: 10947622
    Abstract: The disclosed methods and apparatus improve the fabrication of solid fibers and microstructures. In many embodiments, the fabrication is from gaseous, solid, semi-solid, liquid, critical, and supercritical mixtures using one or more low molar mass precursor(s), in combination with one or more high molar mass precursor(s). The methods and systems generally employ the thermal diffusion/Soret effect to concentrate the low molar mass precursor at a reaction zone, where the presence of the high molar mass precursor contributes to this concentration, and may also contribute to the reaction and insulate the reaction zone, thereby achieving higher fiber growth rates and/or reduced energy/heat expenditures together with reduced homogeneous nucleation. In some embodiments, the invention also relates to the permanent or semi-permanent recording and/or reading of information on or within fabricated fibers and microstructures.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 16, 2021
    Assignee: Dynetics, Inc.
    Inventors: James L. Maxwell, Nicholas Webb, James Allen
  • Patent number: 10946692
    Abstract: A method for manufacturing a printing paper for decorative boards is provided. The method includes the processes of: applying a resin-containing liquid comprising at least one of a resin and a resin precursor to a base paper for decorative boards; forming a print layer on or in the base paper which is not dried after the resin-containing liquid is applied thereto; and solidifying a liquid contained in the base paper having the print layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 16, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Yoshihiro Moriya, Shizuka Kohzuki
  • Patent number: 10950455
    Abstract: A method for manufacturing a semiconductor device in which a semiconductor substrate is provided, including a SOI-wafer having a carrier layer defining a rear side, a functional layer defining a front side. An insulation layer is situated between the carrier layer and functional layer. The functional layer includes a functional area having functional structures. The front side is masked, a first mask opening defines an interior area containing the functional area. The functional layer is removed by etching the front side. The rear side is masked, a second mask opening being configured, and a circumferential edge of the second mask opening is spaced outwardly relative to an outer circumferential edge of the interior area. The carrier layer and the insulation layer are removed at least in the area of the second-mask opening by etching to expose the interior area.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 16, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Zhenyu Wu, Jens Schindele, Torsten Kramer
  • Patent number: 10947605
    Abstract: The invention relates to a method for hydrophobising leather, comprising the steps: providing tanned, at least partly dried leather whose content of free water is in the range of from 0 to 25 wt. %, based on the weight of the dried leather, treating the leather with a mixture of compressed gas and a hydrophobising agent at a pressure of at least 30 bar in a pressure vessel, and relieving the pressure of the pressure vessel to ambient pressure. By using the method according to the invention it is possible to obtain leather which is hydrophobised at the surface, as well as thick and firm, deeply hydrophobised leather, as is used, for example, for shoe soles.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: March 16, 2021
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG DER ANGEWAND
    Inventors: Manfred Renner, Andreas Sengespeick, Michael Prokein, Eckhard Weidner
  • Patent number: 10947413
    Abstract: A process for chemical mechanical polishing cobalt to planarize the surface and remove at least some of the cobalt from a substrate. The process includes providing a polishing composition, containing, as initial components: water; an oxidizing agent; colloidal silica abrasive particles; aspartic acid or salts thereof; a phosphonic acid having an alkyl group of greater than ten carbon atoms, wherein the phosphonic acid having the alky group of greater than ten carbon atoms is included in amounts sufficient to enable high cobalt removal rates of ?2000 ?/min and substantial cobalt corrosion inhibition; and providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the cobalt is polished away and cobalt corrosion is substantially inhibited.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Rohm and Haas Electronic Materials CMP Holdings
    Inventor: Murali Ganth Theivanayagam
  • Patent number: 10941318
    Abstract: To provide a means capable of suppressing the generation of gelation at the time of or after the addition of a silane coupling agent in the production of a cationically modified silica including modifying a silica raw material with a silane coupling agent. The present invention is a method for producing a cationically modified silica, including: mixing a silica raw material having a negative zeta potential with a silane coupling agent having an amino group or a quaternary cationic group; and reacting the silica raw material with the silane coupling agent to obtain a cationically modified silica, in which the cationically modified silica satisfies the following relational expression (1): X<Y??relational expression (1) in the relational expression (1), X is a pH value at which an isoelectric point is shown in the cationically modified silica, and Y is a pH value of the cationically modified silica.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 9, 2021
    Assignee: FUJIMI INCORPORATED
    Inventors: Souma Taguchi, Keiji Ashitaka, Naoya Miwa
  • Patent number: 10928689
    Abstract: A display device includes a substrate of a display panel, including: a display area and a non-display area, an upper surface and a lower surface each in the display area and the non-display area, and side surfaces connecting the upper and lower surfaces to each other; a signal line on the upper surface of the substrate; a circuit substrate on a side surface of the substrate; and a connection electrode on the upper surface of the substrate in the non-display area thereof, where the connection electrode electrically connects the signal line and the circuit substrate to each other. In the non-display area, the substrate further includes: a first etched portion recessed from the side surface at which the circuit substrate is disposed, and a second etched portion extending from the first etched portion toward the signal line, and the connection electrode is in the first and second etched portions.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoungdae Ye, Donghyeon Lee, Junwoo You
  • Patent number: 10926227
    Abstract: A method for fabricating calcite channels in a nanofluidic device is described. A porous membrane is attached to a substrate. Calcite is deposited in porous openings in the porous membrane attached to the substrate. A width of openings in the deposited calcite is in a range from 50 to 100 nanometers (nm). The porous membrane is etched to remove the porous membrane from the substrate to form a fabricated calcite channel structure. Each channel has a width in the range from 50 to 100 nm.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 23, 2021
    Assignee: Saudi Arabian Oil Company
    Inventors: Dong Kyu Cha, Mohammed Badri AlOtaibi, Sultan Muhammad Al Enezi, Ali Abdallah Al-Yousef
  • Patent number: 10930490
    Abstract: Methods for fabricating thin, high-aspect-ratio Ge nanostructures from high-quality, single-crystalline Ge substrates are provided. Also provided are grating structures made using the methods. The methods utilize a thin layer of graphene between a surface of a Ge substrate, and an overlying resist layer. The graphene passivates the surface, preventing the formation of water-soluble native Ge oxides that can result in the lift-off of the resist during the development of the resist.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 23, 2021
    Assignees: Wisconsin Alumni Research Foundation, The Regents of the University of New Mexico
    Inventors: Max G. Lagally, Francesca Cavallo, Vijay Saradhi Mangu
  • Patent number: 10920313
    Abstract: A diazadienyl compound represented by General Formula (I) below: wherein R1 represents a C1-6 linear or branched alkyl group, and M represents nickel atom or manganese atom. In particular, since a compound in which R1 in General Formula (I) is a methyl group has a high vapor pressure and a high thermal decomposition starting temperature, the compound is useful as a raw material for forming a thin film by a CVD method or ALD method.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 16, 2021
    Assignee: ADEKA CORPORATION
    Inventors: Tomoharu Yoshino, Masaki Enzu, Akihiro Nishida, Atsushi Yamashita