Abstract: Since the exposed collector part 32 of one semiconductor switching element 29 is attached to the heat radiating fin 42 by coating and filling a thermal conducting filler therebetween via spacers 33, 34 and 35, and the exposed collector part 37 of another semiconductor switching element 36 is directly attached to the same heat radiating fin 42 by coating the thermal conducting filler 41 thereto without any spacer, heat resulting from switching losses can be effectively transmitted to the heat radiating fin 42 and can be radiated therefrom. To effectively transmit heat, which results from switching losses, to a heat radiating fin and to radiate the same even if two semiconductor switching elements are connected in series, a collector part is exposed on the rear side thereof, and the two semiconductor switching elements are attached to a single heat radiating fin.

Abstract: On a substrate, a first insulating film, a first interlayer insulating film, a second and third insulating films, and a second interlayer insulating film are formed. Wire trenches are formed reaching the upper surface of the third insulating film, and via holes are formed from the bottom of the wire trench to the upper surface of the first insulating film. Formation of the wire trench is performed by etching the second interlayer insulating film under a condition in which the second interlayer insulating film is selectively etched. The third insulating film exposed at the bottoms of the wire trenches and the first insulating film exposed at the bottoms of the via holes are removed by etching under a condition in which the third insulating film is selectively etched. Wires are filled in the via holes and the wire trenches.

Abstract: A semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit and input/output pads suitable for metallurgical contacts. Further, the device has a protective plastic film (polyimide, epoxy resin, or silicone) of controlled and uniform thickness (20 to 60 &mgr;m) selectively attached to the passive surface. The film is suitable to absorb light of visible and ultraviolet wavelengths, to remain insensitive to moisture absorption, and to exert thermomechanical stress on the chip such that this stress at least partially neutralizes the stress exerted by an outside part after chip assembly.

Abstract: A semiconductor device comprises an electrode formed above a substrate, an under bump metal (UBM) film on the electrode, the under bump metal film being in the shape of a recess, and a bump electrode embedded in the under bump metal film, the bump electrode having sides and bottom thereof surrounded by the under bump metal film.

Abstract: A self-aligned semiconductor interconnect barrier between channels and vias is provided which is self-aligned and made of a metallic barrier material. A channel is conventionally formed in the semiconductor dielectric, lined with a first metallic barrier material, and filled with a conductive material. A recess is etched to a predetermined depth into the conductive material, and the second metallic barrier material is deposited and removed outside the channel. This leaves the conductive material totally enclosed in metallic barrier material. The metallic barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof.

Abstract: A radio frequency power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses and protects the semiconductor die. A plurality of leads extend outwardly from the plastic package. The leads have blade-like shapes.

Abstract: A semiconductor package substrate of the present invention includes a first wiring substrate which has an opening section for mounting a semiconductor chip, and a second wiring substrate which has a second wire bonding terminal sections and second connecting terminal land sections, and through holes so that the second connecting terminal land sections on the first surface communicate to the second surface which is opposite to the first surface. The second surface of the first wiring substrate and the first surface of the second wiring substrate are mated in the state where the second wire bonding terminal sections are exposed. The semiconductor package substrate is suitable for a stacked semiconductor package, and capable of dense mounting. Also, it provides a stable and ensured mouting, thereby increasing the yield of the stacked semiconductor package.

Abstract: A semiconductor device and method of making the same includes a first metallization level, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer and the first etch stop layer. The first etch stop layer is disposed over the first metallization level. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. Dopants are introduced into the metal and are activated by laser thermal annealing. A concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature, and a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature.

Abstract: A semiconductor device includes a two-part, coplanar, interdigitated decoupling capacitor formed as a part of the conductive lead frame. For down-bonded dice, the die attach paddle is formed as the interdigitated member. Alternatively, an interdigitated capacitor may be placed as a LOC type lead frame member between electrical bond pads on the die. The capacitor sections comprise Vcc and Vss bus bars.

Abstract: In a case that a bare chip has been detected as being defective from among bare chips, a good chip is mounted to the rear surface of the surface wherein the bare chips are provided to a semiconductor module substrate so that a QFC pin of the bare chip is fixed at the ground potential (GND). Thereby, the bare chip stops the output of a signal to the input/output terminals or the input of a signal from the input/output terminals. As a result, the good chip outputs an electrical signal to the input/output terminals or an electrical signal is inputted from the input/output terminals. Thereby, a semiconductor module is gained that can be repaired even in the case that a defective chip is detected after the chip has been molded into a mold resin.

Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.

Abstract: A power device compatible with an SOT 227 package standard. The device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The first conductive layer has been patterned to provide at least first and second conductive blocks. A semiconductor die is bonded to the first block of the first conductive layer of the substrate. A terminal lead is coupled to the second block of the first conductive layer of the substrate.

Abstract: A semiconductor device includes a semiconductor chip, an insulating layer formed on a region excluding the plurality of electrode pads on the principal surface of the semiconductor chip, a plurality of contact pads arranged on the insulating layer, a wiring layer electrically connected to at least one of the plurality of electrode pads and electrically connected to at least one of the plurality of contact pads, thereby establishing rewiring connection, an insulative resin layer formed on a region excluding the plurality of contact pads on the principal surface of the semiconductor chip, a protruded electrode provided on each of the plurality of contact pads, and an underfill material layer provided on the insulative resin layer in such a manner that the top of the protruded electrode is exposed.

Abstract: An integrated circuit including a die, a first conductor electrically coupled to the die, a second conductor and a conductive liquid that electrically couples the first conductor (e.g., a pin) to the second conductor (e.g., a socket) to lower the resistance between the first conductor and the second conductor.

Abstract: A power semiconductor module in which a main circuit terminal lead frame part and a control circuit lead frame part are bent toward a main circuit lead frame part, is provided. The power semiconductor module includes a main circuit part; a control circuit part and a control circuit terminal which are placed along a plane perpendicular to the main circuit part; a main circuit terminal placed along another plane perpendicular to the main circuit part, facing the control circuit part the control circuit terminal; a bonding wire; and a mold compound. Accordingly, it is possible to realize a light and compact intelligent power module that is simple to manufactured at a low cost.

Abstract: An electronic component is formed with at least two semiconductor chips that are disposed on a carrier substrate. Active chip surfaces of the semiconductor chips include central contact surfaces on which opposing solder contact surfaces are formed. These are conductively connected to an intermediate carrier which is disposed between the semiconductor chips and which produces rewirings from them to the carrier substrate. A method for fabricating the component is also described.

Abstract: A structure for using fuse structure integrated wire bonding on the substrate, and relates to methods for making the same are disclosed, in which an Al-fuse has an extra-etching process pattern by fuse-open mask and has been thinned down from Al-fuse thickness. The Al fuse structure integrated Al wire-bonding pad has two kind of thickness under fuse-open and for the other area. This invention makes the fuse easy to blow without suffering any bondability from wire bonding for packaging.

Abstract: A package stacked semiconductor device includes a plurality of pin linking means for electrically connecting at least one of control signal pins of one package to its neighbor NC pin of the same package. Either of the control signal pin or the neighbor NC pin, which are electrically interconnected, is electrically connected to the corresponding pin of the next package.

Abstract: Wires are formed on the main surface of a semiconductor substrate via a silicon oxide film. A nitride film is formed on the wires and the upper edge corner parts of the nitride film are rounded. Another nitride film, covering the nitride film, is formed and an interlayer oxide film is formed so as to cover this film. Contact holes are formed in the interlayer oxide film which reach the nitride film as well as the main surface of the semiconductor substrate and plug parts are formed within those contact holes.

Abstract: A high gain phototransistor uses lateral and vertical transistor structures and a triple base. The base regions of two vertical structures are in the bulk of a semiconductor substrate while the base of a single lateral structure is adjacent a light receiving phototransistor surface. Minority carrier generation extends from the base region of the lateral transistor to the base regions of the vertical transistors and is present in the vertical regions within a diffusion length of the optically generated carriers of the lateral base. The bases of all three transistor structures are electrically connected. The collector electrodes of one of the vertical structures and the lateral structure are electrically connected, while the emitter electrodes of the other of the vertical structures and the lateral structures are electrically connected. Finally, the remaining vertical collector and emitter electrodes are electrically connected via a buried layer adjacent the phototransistor wafer substrate.