Abstract: A semiconductor device comprises: a semiconductor chip; a copper series lead frame with no residual of a rustproof film, including a die pad mounted with said semiconductor chip, and a plurality of leads disposed so that inner ends of said leads are positioned along the periphery of said die pad; copper wires to directly connect electrodes on said semiconductor chip to the inner ends of said plurality of leads; and a resin molded member to hermetically seal said semiconductor chip, a large proportion of said lead frame and said copper wires, wherein a water soluble rustproof agent is applied over outer lead segments, protruding from said resin molded member, of said plurality of leads.

Abstract: A semiconductor package is comprised of a substrate for mounting and fixing a semiconductor element thereon and a connecting pattern. The substrate is provided with a through hall formed therein. The semiconductor element is fixed with its surface where the element is formed being mounted on the substrate and with its electrode being within the through hall. The electrode of the semiconductor element is electrically connected to the connecting pattern via wires through the through hall. The through hall and the wires are sealed with resin.

Abstract: A lead frame for a surface mount semiconductor chip package includes a die attach paddle and leads, the die attach paddle having down bond attachment sites on an upper surface of the paddle near a peripheral margin of the paddle, and having a central die attach region on an upper surface of the paddle, wherein a portion of the upper surface of the paddle is recessed. In some embodiments the recessed portion of the upper surface of the paddle includes the die attach region, and in other embodiments the recessed portion of the upper surface of the paddle includes a groove. Also, a lead frame surface mount chip package including such a lead frame.

Abstract: Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Preferably, a nitrogen content is graded within a thickness of the dielectric layer to provide an upper lying nitrogen rich contiguous surface layer of the dielectric layer and a lower lying nitrogen poor contiguous layer of the dielectric layer. The method contemplates a microelectronic fabrication having formed therein a dielectric layer formed in accord with the method. The method provides the resulting dielectric layer with a lower dielectric constant and enhanced adhesion properties as a substrate layer.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: A semiconductor chip package with direction-flexible mountability comprising a switching circuit for switching a pin function according to the mounting direction of a package, a pair of pin-definition pins for defining the pin function and a pair of power supply leads, and a pair of ground leads. One of the power supply lead pair and the ground lead pair is rotation-symmetrical to the other, respectively. The semiconductor chip package with direction-flexible mountability in accordance with the present invention eliminates a process for indicating the mounting direction because the package can be mounted onto a substrate regardless the direction. Accordingly, the ID pin indication and a series of processes for testing the ID pin are eliminated and the malfunction due to the incorrect direction is prevented.

Abstract: Provided are a composite material excellent in plastic workability, a method of producing the composite material, a heat-radiating board of a semiconductor equipment, and a semiconductor equipment to which this heat-radiating board is applied. This composite material comprises a metal and an inorganic compound formed to have a dendritic shape or a bar shape. In particular, this composite material is a copper composite material, which comprises 10 to 55 vol. % cuprous oxide (Cu2O) and the balance of copper (Cu) and incidental impurities and has a coefficient of thermal expansion in a temperature range from a room temperature to 300° C. of from 5×10−6 to 17×10−6/° C. and a thermal conductivity of 100 to 380 W/m·k. This composite material can be produced by a process comprising the steps of melting, casting and working and is applied to a heat-radiating board of a semiconductor article.

Abstract: A semiconductor device includes a SAW device chip. The SAW device chip is provided on a passive element chip in which a passive element circuit including a transmission line is formed on a semi-insulating compound substrate having one surface set to have a ground potential electrode. In the semiconductor device, even when the width of the transmission line is increased, a high characteristic impedance can be maintained by increasing the thickness of the substrate. This can reduce the resistance of the transmission line and can facilitate matching with the SAW device.

Abstract: An apparatus, system and method for fabricating a wafer utilizing a dual damascene process are described. A wafer-in-process, having conductive plugs within a first dielectric layer, a hard mask over the first dielectric layer, vias in a second dielectric layer which overlies the hard mask, and a photoresist material within the vias is further processed by a photolithographic device having transparent portions and radiant energy inhibiting portions. The photolithographic device is registered to the wafer-in-process to prevent radiant energy from being directly transmitted into the photoresist material overlaying the vias. This prevents the exposure of a portion of the photoresist material at a lower portion of the vias, thus protecting the hard mask layer and/or the conductive plugs from damage during a subsequent etching process. The exposed photoresist material is then removed.

Abstract: A semi-insulating bulk single crystal of silicon carbide is disclosed that has a resistivity of at least 5000 &OHgr;-cm at room temperature and a concentration of deep level trapping elements that is below the amounts that will affect the resistivity of the crystal, preferably below detectable levels. A method of forming the crystal is also disclosed, along with some resulting devices that take advantage of the microwave frequency capabilities of devices formed using substrates according to the invention.

Abstract: A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

Abstract: A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.

Abstract: On a surface of a pair of support leads formed in one piece with a die pad on which a semiconductor chip is mounted, a protrusion is formed on the side that the semiconductor chip is mounted. During a resin-sealing, a lower surface of the die pad is brought into contact with an internal wall surface of a lower die, while a top of the protrusion is brought into contact with an internal wall surface of an upper die. This makes it possible to prevent the displacement of the die pad during sealing, thus causing no residual distortion of the semiconductor chip. As a result, a semiconductor device with a stable quality can be obtained.

Abstract: A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence.

Abstract: Provided are a composite material excellent in plastic workability, a method of producing the composite material, a heat-radiating board of a semiconductor equipment, and a semiconductor equipment to which this heat-radiating board is applied. This composite material comprises a metal and an inorganic compound formed to have a dendritic shape or a bar shape. In particular, this composite material is a copper composite material, which comprises 10 to 55 vol. % cuprous oxide (Cu2O) and the balance of copper (Cu) and incidental impurities and has a coefficient of thermal expansion in a temperature range from a room temperature to 300° C. of from 5×10−6 to 17×10−6/° C. and a thermal conductivity of 100 to 380 W/m·k. This composite material can be produced by a process comprising the steps of melting, casting and working and is applied to a heat-radiating board of a semiconductor article.

Abstract: To provide a semiconductor device restraining high frequency impedance and restraining deterioration of a semiconductor layer, a gate wiring 26 is extended while meandering and intersects with a substantially straight line portion of a semiconductor layer 02 by a plurality of times thereby providing a plurality of gates.

Abstract: Techniques for maintaining the optical coupling efficiency between photonic devices of an optoelectronic module and its interconnecting optical fibers are described. The techniques ensure that the mating surfaces of an optical sub-assembly and a chip sub-assembly remain planar to each other throughout and after the soldering process of the optoelectronic manufacturing process. These techniques include the use of a ceramic fixture made of a stack of plates having openings that secure the orientation of the optical and chip sub-assemblies. The fixture can have one or more openings to secure a respective one or more combination of optical and chip sub-assemblies. A high temperature tape can also be used to maintain the parallelism between the optical and chip sub-assemblies. An optical sub-assembly having pedestals on its bottom surface can also be use to maintain parallelism of the optical and chip sub-assemblies. Methods of using each technique is also described.

Abstract: A semiconductor package includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads which each have an inner end disposed adjacent the peripheral edge in spaced relation thereto and an opposing distal end. The package includes at least one isolated ring structure electrically connected to the semiconductor chip and at least one of the leads. The ring structure includes a main body portion disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto, and at least one stub portion extending angularly from the main body portion along one of the leads in spaced relation thereto.

Abstract: An integrated circuit capacitor includes a silicon-on-insulator (SOI) substrate and a doped epitaxial layer of a first conductivity type formed on the SOI substrate. The doped epitaxial layer is used as a first plate of the integrated circuit capacitor. A gate oxide layer is formed on the doped epitaxial layer and is used as a dielectric layer of the integrated circuit capacitor. A polysilicon gate is formed on the gate oxide layer and is used as a second plate of the integrated circuit capacitor.

Abstract: A millimeter wave (MMW) transceiver module includes a microwave monolithic integrated circuit (MMIC) transceiver chip set that is surface mounted on a circuit board. The MMIC transceiver chip set includes a receiver MMIC chip package, a transmitter MMIC chip package, and a local oscillator (LO) multiplier MMIC chip package. Each MMIC chip package includes a base and a multilayer substrate board formed from layers of low temperature transfer tape. The multilayer substrate board has at least three layers and carries RF signals, DC signals, grounding and embedded passive components, including resistors and capacitors. At least one MMIC chip is received on the multilayer substrate board.