Patents Examined by Sonya D. McCall-Shepard
  • Processes for making reliable VCSEL devices and VCSEL arrays
    Patent number: 9520696
    Abstract: A set of VCSEL fabrication methods has been invented which enhance the performance and long time reliability of VCSEL devices and arrays of devices. Wafer bow caused by growing a large number of epitaxial layers required to fabricate VCSEL device generates strain and results in bowing/warping of the device wafer. The stress so generated is eliminated by applying a stress compensation layer on the substrate to a surface opposite to the epitaxial layer surface. New oxidation equipment designs and process parameters are described which produce more precision apertures and reduce stress in the VCSEL device. An ultrathin fabrication procedure is described which enables high power VCSELs to be made for high power operation at many different wavelengths. A low temperature electrical contacting process improves VCSEL long term reliability.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 13, 2016
    Assignee: PRINCETON OPTRONICS INC.
    Inventors: Qing Wang, Jean-Francois Seurin, Chuni L Ghosh, Laurence S Watkins
  • Method for making high voltage integrated circuit devices in a fin-type process and resulting devices
    Patent number: 9520396
    Abstract: Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Fin end spacer for preventing merger of raised active regions
    Patent number: 9515168
    Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
  • Method for manufacturing semiconductor device
    Patent number: 9508564
    Abstract: A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Yokoyama, Kazuyo Endo, Jun Fujita, Shinnosuke Soda, Kazuyasu Nishikawa, Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue
  • Methods and apparatus for MEMS devices with increased sensitivity
    Patent number: 9505605
    Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Integrated circuits and fabrication methods thereof
    Patent number: 9508786
    Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 29, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
  • Method for manufacturing liquid crystal display device
    Patent number: 9502613
    Abstract: The present invention provides a method for manufacturing a liquid crystal display device capable of reducing thermal damage to a polarizing plate during thermo-compression bonding, thereby sufficiently preventing the occurrence of defects due to the deformation of the polarizing plate. The method for manufacturing a liquid crystal display device according to the present invention is for thermo-compression bonding a terminal portion of a liquid crystal panel and an external circuit using a pressure bonding device configured of a stage, a heat source, and a buffer member. The manufacturing method includes placing the liquid crystal panel on the stage, and thermo-compression bonding the terminal portion of the liquid crystal panel and the external circuit by heat from the heat source via the buffer member interposed between the heat source and the external circuit.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 22, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuhiko Sugihara, Takeyuki Ashida
  • Non-planar quantum well device having interfacial layer and method of forming same
    Patent number: 9502568
    Abstract: Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Robert S. Chau
  • Integrated device package comprising a magnetic core inductor with protective ring embedded in a package substrate
    Patent number: 9496213
    Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Donald William Kidwell, Jr., Ravindra Shenoy, Mete Erturk, Layal Rouhana
  • Semiconductor device having metal gate and manufacturing method thereof
    Patent number: 9490334
    Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Light source module and backlight unit including the same
    Patent number: 9470839
    Abstract: Provided are a light source module and a backlight unit. According to an embodiment, the light source module comprises a circuit board, at least one LED chip electrically connected onto the circuit board, a reflective surface on an upper surface of the LED chip configured to reflect light, and a fluorescent surface on at least one side surface of the LED chip configured to emit the light.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: October 18, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung Dae Ye, Young Chun Kim, Hyuk Hwan Kim
  • Method of manufacturing solid-state imaging apparatus
    Patent number: 9466639
    Abstract: A method of manufacturing a solid-state imaging apparatus, comprising preparing a substrate on which photoelectric conversion portions are arranged, forming inner lenses corresponding to the photoelectric conversion portions, and forming microlenses corresponding to the photoelectric conversion portions, wherein the forming inner lenses includes forming, on the substrate, a dielectric film for forming the plurality of inner lenses, and etching second portions of the dielectric film around first portions serving as central portions of the inner lenses while leaving upper faces of the first portions, so as to form curved faces or inclined faces connected to the upper faces.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 11, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yusuke Tsukagoshi
  • Image sensors including well regions of different concentrations and methods of fabricating the same
    Patent number: 9466636
    Abstract: An image sensor includes a high concentration well region in contact with a device isolation layer extending along a periphery of a photoelectric converting part, which can improve dark current properties of the image sensor. The image sensor also includes a low concentration well region in contact with a sidewall of the device isolation layer overlapped with a transfer gate, which can improve image lag properties of the image sensor. Related fabrication methods are also discussed.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 11, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungchak Ahn, Yitae Kim
  • Conductor pattern forming method, and semiconductor device manufacturing method
    Patent number: 9466485
    Abstract: A conductor pattern forming method includes forming, on a conductor film, a laminated film including a first layer thinner than the conductor film, a second layer thicker than the first layer, and a third layer thinner than the second layer, which layers are laminated in order from the conductor film side. A first mask is formed from the third layer by dry-etching the third layer using a photoresist mask formed on the laminated film. A second mask is formed from the second layer by dry-etching the second layer using the first mask. The conductor film is exposed by dry-etching the first layer using the second mask. A conductor pattern is formed from the conductor film by dry-etching the conductor film using the second mask.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: October 11, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keita Torii
  • Interconnect structure for an integrated circuit and method of fabricating an interconnect structure
    Patent number: 9466563
    Abstract: An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second metallization level includes a dielectric layer having a via opening formed therein extending vertically through the dielectric layer to reach a top surface of the first metal routing path. A metal plug is deposited at a bottom of the via opening in direct contact with the first metal routing path. A remaining open area of the via opening is filled with a metal material to define a second metal routing path. The metal plug is formed of cobalt or an alloy including cobalt, and has an aspect ratio of greater than 0.3.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: October 11, 2016
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann Mignot, Terry Spooner, James John Kelly
  • Solid state imaging apparatus and method of producing the same
    Patent number: 9461082
    Abstract: There is provided a solid state imaging apparatus, including: an optical film layer on which a solid state image sensor is mounted; a multifunctional chip laminated at a periphery of the solid state image sensor in the optical film layer being electrically contacted with the optical film layer via a metal body; a sealing resin layer for sealing the periphery where the multifunctional chip is laminated on the optical film layer; and a concave structure for blocking a flow of the sealing resin in a liquid state when the sealing resin layer is formed at the periphery of the sealing resin layer. Also, a method of producing the solid state imaging apparatus is also provided.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: October 4, 2016
    Assignee: Sony Corporation
    Inventor: Masataka Maehara
  • Method of manufacturing semiconductor device
    Patent number: 9460929
    Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.
    Type: Grant
    Filed: February 28, 2015
    Date of Patent: October 4, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromasa Yoshimori, Hirofumi Tokita
  • Light-emitting element, light-emitting device, electronic device, and lighting device
    Patent number: 9461273
    Abstract: A light-emitting element having high external quantum efficiency is provided. A light-emitting element having a long lifetime is provided. A light-emitting element includes a light-emitting layer between a pair of electrodes. The light-emitting layer contains at least a phosphorescent compound, a first organic compound (host material) having an electron-transport property, and a second organic compound (assist material) having a hole-transport property. The light-emitting layer has a stacked-layer structure including a first light-emitting layer and a second light-emitting layer, and the first light-emitting layer contains a higher proportion of the second organic compound than the second light-emitting layer. In the light-emitting layer (the first light-emitting layer and the second light-emitting layer), a combination of the first organic compound and the second organic compound forms an exciplex.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 4, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromi Seo, Satoko Shitagaki, Satoshi Seo, Takahiro Ushikubo, Toshiki Sasaki, Shogo Uesaka
  • Etching method for reducing microloading effect
    Patent number: 9443741
    Abstract: An etching method includes forming a high density structure and a low density structure on a substrate. A first material layer is formed to cover both structures. Part of the low density structure is exposed through the first material layer. A second material layer is formed to cover the first material layer. The second material layer is etched to remove the second material layer on the high density structure and part of the second material layer on the low density structure. The first material layer on the high density structure and the second material layer on the low density structure are simultaneously etched. The first material layer is etched to expose a first portion of the high density structure and a second portion of the low density structure. Finally, the first portion and the second portion are removed.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhi-Jian Wang, Cheng-Chang Wu, Hsin-Yu Hsieh, Shui-Yen Lu
  • Chip packages and methods of manufacturing the same
    Patent number: 9443806
    Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a chip package may include: a chip having a contact pad disposed at a first side of the chip; a passivation layer over the first side of the chip, the passivation layer having an opening disposed over the contact pad; a polymer layer over the passivation layer, the polymer layer having an edge disposed over the contact pad; a conductive structure formed atop the contact pad, the conductive structure filling the opening of the passivation layer and covering the edge of the polymer layer; and a frontside redistribution layer (RDL) disposed over the conductive structure, the frontside RDL having a first portion electrically connected to the conductive structure and a second portion electrically connected to the first portion and extending laterally away from the first portion and the conductive structure.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Cheng-Chieh Hsieh, Tsung-Shu Lin, Chen-Hua Yu