Abstract: In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.

Abstract: An electronic component package includes: a core including a cavity, a first resin layer, a second resin layer and a reinforcing layer disposed between the first resin layer and the second resin layer; and an electronic component disposed in the cavity, wherein a thickness of the first resin layer is different from a thickness of the second resin layer.

Abstract: An integrated circuit package assembly includes a substrate and a first integrated circuit package over the substrate. The integrated circuit package assembly also includes a second integrated circuit package between the first integrated circuit package and the substrate. The integrated circuit package further includes solder bumps between the first integrated circuit package and the second integrated circuit package. The solder bumps are configured to electrically connect the first integrated circuit package and the second integrated circuit package. The integrated circuit package assembly further includes at least two support structures between and in direct contact with the second integrated circuit package and the substrate. The at least two support structures are configured to facilitate thermal conduction between the second integrated circuit package and the substrate without providing electrical connections.

Abstract: Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: A method for fabricating a vertical Schottky barrier transistor includes forming fin trenches through a dielectric layer and a dummy gate stack on a substrate to expose an underlying semiconductor material. The dummy gate stack includes a bottom spacer, a dummy gate layer and a top spacer layer. Fins are epitaxially grown in the fin trenches from the underlying semiconductor material. The dummy gate layer is removed and forms a gate structure about the fins including a gate dielectric and a gate conductor. An interlevel dielectric (ILD) layer is deposited. A top of the fins is exposed to form a channel contact opening. A contact trench is formed through the ILD layer and into the underlying semiconductor material. A cavity is formed in the underlying semiconductor material below the bottom spacer layer. The cavity, the contact trench and the channel contact opening are filled with a conductive fill.

Abstract: A semiconductor device includes a semiconductor substrate and a first semiconductor element. The semiconductor substrate has a circuit core area. The first semiconductor element is arranged on the semiconductor substrate and at least partially surrounds the periphery of the circuit core area. A layout area of the first semiconductor element is larger than a layout area of any of the semiconductor elements in the circuit core area.

Abstract: Carbon-doped germanium stressor regions are formed in an nFET device region of a germanium substrate and at a footprint of a functional gate structure. The carbon-doped germanium stressor regions are formed by an epitaxial growth process utilizing monomethylgermane (GeH3—CH3) as the carbon source. The carbon-doped germanium stressor regions that are provided yield more strain in less volume since a carbon atom is much smaller than a silicon atom.

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region is provided. A first semiconductor region is formed over a second semiconductor region and with a first doping type. The second semiconductor region has a second doping type different than the first doping type. A gate electrode is formed laterally adjacent to the first semiconductor region and extending along a side boundary of the first semiconductor region. A first source/drain contact region and a second source/drain contact region are respectively formed on opposite sides of the gate electrode and with the second doping type. The first source/drain contact region is further formed over the first semiconductor region. A method for manufacturing the LDMOS transistor is also provided.

Abstract: A system and method for vertically integrating heterogeneous devices into a 3D tile architecture are disclosed. The system uses high precision microelectronics fabrication techniques and known-good-die to achieve high yield to integrate devices to process radio frequency signals at microwave frequencies of approximately 300 MHz to 300 GHz and above. The inventive architecture is based on a high density of small diameter vias to manage the integrity of electrical interconnects and simplify electrical routing.

Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

Abstract: In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.

Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.

Abstract: A method of forming a vertical FET device and a horizontal FINFET device on a common semiconductor substrate includes forming, on the semiconductor substrate, vertical device fins for the vertical FET device and the horizontal FINFET device with a sacrificial layer and a hard mask (HM) layer. The method also includes forming a vertical FET device doped source and drain (S/D) on the substrate, forming a shallow trench isolation (STI) and a bottom spacer, removing the HM layer and the sacrificial layer for horizontal FINFET device, and forming a sacrificial gate. The method further includes forming an oxide inter dielectric (ILD) layer, and opening the sacrificial gate, forming high-k vertical FET device gate and a high-k horizontal FINFET device gate, and forming contacts.

Abstract: An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract: A method of manufacturing a semiconductor device includes receiving film thickness distribution data of a polished first insulating film of a substrate; calculating processing data for reducing a difference between a film thickness at a center side of the substrate and a film thickness at a periphery side of the substrate, based on the film thickness distribution data; loading the substrate into a process chamber; supplying a process gas to the substrate; and correcting a film thickness of the first insulating film based on the processing data by activating the process gas so that a concentration of active species of the process gas generated at the center side of the substrate differs from a concentration of active species of the process gas generated at the periphery side of the substrate.

Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A device comprises a first chip comprising a plurality of first interconnect structures over a first substrate, a plurality of first connection pads over the plurality of first interconnect structures and a plurality of first bonding pads, wherein a first bonding pad is formed over a corresponding first connection pad, and a second chip comprising a plurality of second interconnect structures over a second substrate and a plurality of second bonding pads over the plurality of second interconnect structures, wherein the first chip and the second chip are face-to-face bonded together, and wherein a first bonding pad is in direct contact with a corresponding second bonding pad.