Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate. The chip package also includes a lid over the semiconductor die. The lid has a number of support structures bonded with the substrate, and the lid has one or more openings between two of the support structures.

Abstract: Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.

Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.

Abstract: The invention relates to a method for manufacturing an electronic device, particularly a device including a flexible and/or low-cost substrate and/or carbon nanotubes, and also relates to electronic devices produced using said method.

Abstract: A method comprises depositing a first dielectric layer over a first chip comprising a plurality of first active circuits and a first connection pad, patterning the first dielectric layer to form a first opening, filling the first opening to form a connector in contact with the first connection pad, depositing a second dielectric layer over the first dielectric layer, patterning the second dielectric layer to form a second opening over the connector, filling the second opening to form a first bonding pad in contact with the connector, stacking a second chip on the first chip, wherein the second chip comprises a plurality of second active circuits and a second bonding pad and bonding the first chip and a second chip together to form a stacked semiconductor device through applying a hybrid bonding process to the first bonding pad and the second bonding pad.

Abstract: An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO3(ZnO)m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Abstract: A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on first surface of the lowermost layer, a conductor post having upper surface facing the first surface of the lowermost layer, a metal post formed such that the metal post is protruding from second surface of the lowermost layer and is positioned at lower surface of the conductor post, an electronic component embedded in the lowermost layer such that the component is positioned on second surface side of the lowermost layer and has an electrode facing the first surface of the lowermost layer, and via conductors formed in the lowermost layer and including first and second via conductors such that the first via conductor is connecting the first conductor layer and the upper surface of the conductor post and the second via conductor is connecting the first conductor layer and the electrode of the component.

Abstract: A display device includes a first pixel, a second pixel, a first substrate, and a second substrate. The first pixel includes a first pixel electrode, a first conductive film, and a first transistor. The first pixel electrode is electrically connected to the first transistor. The first conductive film includes a region functioning as a common electrode. The second pixel includes a second pixel electrode, a second conductive film, and a second transistor. The second pixel electrode is electrically connected to the second transistor. The second conductive film includes a region functioning as a common electrode. The first conductive film and the second pixel electrode are provided on the same plane. A first insulating film is provided over the first conductive film and the second pixel electrode. The first pixel electrode and the second conductive film are provided over the first insulating film.

Abstract: A semiconductor substrate contains a plurality of semiconductor die with a saw street between the semiconductor die. A plurality of bumps is formed over a first surface of the semiconductor die. An insulating layer is formed over the first surface of the semiconductor die between the bumps. A portion of a second surface of the semiconductor die is removed and a conductive layer is formed over the remaining second surface. The semiconductor substrate is disposed on a dicing tape, the semiconductor substrate is singulated through the saw street while maintaining position of the semiconductor die, and the dicing tape is expanded to impart movement of the semiconductor die and increase a space between the semiconductor die. An encapsulant is deposited over the semiconductor die and into the space between the semiconductor die. A channel is formed through the encapsulant between the semiconductor die to separate the semiconductor die.

Abstract: A pixel structure of an image sensor and fabrication methods thereof are provided. The pixel structure includes a semiconductor substrate and plural pixel units disposed on the semiconductor substrate. The pixel units are electrically connected to each other, and each of the pixel units includes a light-sensitive region, a transfer gate and a protection layer. A terminal portion of the protection layer is covered by the transfer gate, and a width of the terminal portion of the protection layer is progressively decreased along a depthwise direction of the terminal portion of the protection layer. In the fabrication methods of the pixel structure, the protection layers of the pixel units are formed by doping with a tilt angle, so as to form the terminal portion of the protection layer.

Abstract: A display device includes a gate line; first and second adjacent data lines intersecting the gate line; a first sub-pixel electrode between the first and second data lines; a second sub-pixel electrode between the first gate line and the first sub-pixel electrode; a first switching element connected to the first gate line, the first data line and the first sub-pixel electrode; a second switching element connected to the first gate line, the first data line and the second sub-pixel electrode; a connection electrode connecting the first sub-pixel electrode and the first switching element; a first dummy electrode between the first data line and the second sub-pixel electrode; and a second dummy electrode extending from the connection electrode and is disposed closer to the first data line than the second data line. End portions of the first and second dummy electrodes face each other.

Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.

Abstract: A packaging process of an electronic component includes the following steps. Firstly, a semi-package unit is provided. The semi-package unit includes a first insulation layer and an electronic component. The electronic component is partially embedded within the first insulation layer. The electronic component includes at least one conducting terminal. Then, a metal layer is formed over the surface of the semi-package unit and a part of the metal layer is removed, so that a metal mask is formed on the surface of the semi-package unit and the at least one conducting terminals is exposed. Then, a metal re-distribution layer is formed on the metal mask and the at least one conducting terminal. Then, a part of the metal re-distribution layer and a part of the metal mask are removed, so that at least one contact pad corresponding to the at least one conducting terminal is produced.

Abstract: A resin composition has a high glass transition temperature and is highly adhesive to a member made of metal, ceramics, or the like. The resin composition includes a thermosetting base resin, a thermoplastic resin powder, a curing agent, and an inorganic filler, a cured resin product formed by curing the resin composition, and an electrical member.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.