Abstract: To improve the characteristics of a semiconductor device having a substrate contact formed in a deep trench. In a method of forming a plug PSUB in a deep trench DT2 that penetrates an n-type buried layer NBL and reaches a p-type epitaxial layer PEP1, the plug PSUB is formed in the deep trench DT2 after a metal silicide layer SIL1 is formed in the p-type epitaxial layer PEP1. The metal silicide layer SIL1 is formed using a PVD-first metal film (a first metal film formed by PVD). A first barrier metal film BM1 at the bottom of the plug PSUB is a CVD-second metal film (a second metal film formed by CVD). The first metal film is a metal film different from the second metal film.

Abstract: A method of forming semiconductor elements in an artificial neural network, the method including forming a substrate including an oxide layer, forming a Silicon layer on the oxide layer, depositing a thin film dopant layer on the Silicon layer, and controlling a concentration of the dopant in the thin film dopant layer.

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Abstract: Electrical short caused by misalignment of source select level contact via structure and support pillar structures can be prevented by modifying the pattern of the support pillar structures such that the support pillar structures are omitted from the area in which source select gate contact via structures are formed. The insulating layer at the level overlying the source select level electrically conductive layer can have a sufficient thickness to prevent deformation during formation of the backside recesses. A minimum lateral separation distance between the source select level contact via structure and the support pillar structures is greater than any minimum lateral separation distance between the word line level contact via structures and the support pillar structures.

Abstract: Embodiments of the invention pertain to methods useful in transfer printing of small objects, like micro-LEDs from one substrate to another using acoustic or ultrasonic energy. The pickup of objects from a substrate is performed by transfer head equipped with sticky polymer and an array of ultrasonic transducers, and the high efficiency and selectivity of pickup of selected objects is done using ultrasonic energy directed towards the object. The disposing of objects to another substrate from a transfer head is done by directing an ultrasonic energy toward an object, which enable effective and selective detachment of an object from a sticky polymer. Yet another embodiment also uses a UV light source, which directs the light to the UV curable liquid disposed around the object on receiving substrate, thus curing this liquid would attach an object to receiving substrate.

Abstract: A capacitor array structure which includes N capacitor units is provided. Each capacitor unit includes a first metal layer, a second metal layer, and a third metal layer to form an upper electrode and a lower electrode. The second metal layer is disposed between the first metal layer and the third metal layer, and includes a second patterned metal portion of the lower electrode and a first patterned metal portion of the upper electrode. disposed above. The second patterned metal portion of the lower electrode has an opening, and a side of the first patterned metal portion of the upper electrode is exposed in the opening, such that the side of the first patterned metal portion of the upper electrode is adjacent to the lower electrode of another capacitor unit.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor portion, and an insulating portion. The insulating portion is provided in the stacked body and extends in a stacking direction and a first direction along a surface of the substrate, the first direction crossing the stacking direction. The insulating portion includes a first insulating film containing silicon oxide, a second insulating film containing silicon oxide, and a third insulating film located between the first insulating film and the second insulating film and containing silicon nitride.

Abstract: The present disclosure is provided a display device. The display device includes subpixels and at least one scan line. The subpixels are formed on a first substrate, and each of the subpixels includes an emission area, in which a light emitting element for emitting light is disposed, and a circuit area in which a circuit for driving the light emitting element is disposed. The at least one scan line may be disposed on the circuit area in a horizontal direction. The at least one scan line may include: an upper scan line and a lower scan line spaced apart from each other; and a scan connection line positioned between the upper scan line and the lower scan line and electrically connecting the upper scan line and the lower scan line.

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

Abstract: A method of forming a power rail to semiconductor devices that includes forming a gate structure extending from a first active region to a second active region of a substrate, and removing a portion of the gate structure forming a gate cut trench separating the first active region from the second active region. A fill material of an alternating sequence of at least two different composition conformally deposited dielectric layers is formed within the gate cut trench. A power rail is formed in the gate cut trench. An aspect ratio of the vertically orientated portions of the alternating sequence of the at least two different composition conformally deposited dielectric layer obstructs lateral etching of the gate cut trench during etching to form a power rail opening for housing the power rail.

Abstract: The present disclosure provides a light-emitting unit and a display device. The light-emitting includes a micro-LED element and a bonding pad. The micro-LED element includes an element pin, the bonding pad includes a bonding pin, in each welding pair of the element pin and the bonding pin, a length of the element pin is greater than a width of the bonding pin, and a non-zero angle is formed between the extending direction of the element pin and the extending direction of the bonding pin. When the element pin is deviated from the bonding pin in a certain range, the element pin can still be aligned accurately with the bonding pin. Thus, a requirement on the alignment precision between the micro-LED element and the bonding pad is lowered in a certain extent, thereby improving the yield.

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Abstract: A thin film transistor (TFT) structure is provided herein, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. The light-shielding resin has functions of light-shielding and insulation. With doping through two through holes at two sides, the manufacturing process is simplified, the exposure process is simplified, the production time is shortened, the usage of masks is decreased, and the production cost is lowered.

Abstract: An apparatus for processing a wafer includes a process chamber, a wafer support, a heat source, and a movable device. The wafer support is in the process chamber. The heat source is in the process chamber. The movable device contacts the heat source, in which the movable device is movable with respect to the wafer support.

Abstract: In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.

Abstract: A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.

Abstract: A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.

Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.

Abstract: A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.