Abstract: A digital/analog hybrid frequency synthesizer having a digital frequency synthesizer for digitally generating an analog output signal of a predetermined frequency within a frequency range of f to f+.DELTA.f; an input stage analog frequency synthesizer for, receiving the digital frequency synthesizer output signal and I analog input stage input signals, each input stage input signal separated in frequency from a next one by a frequency increment of .DELTA.f wherein a first one and a last one of the input stage input signals are respectively of a frequency of f.sub.A and f.sub.A +(I-1).DELTA.

Abstract: In a supertwist type liquid crystal display device using a supertwist type liquid crystal display cell and an optical compensation plate made of phase difference plates of uniaxial oriented polymer film, the phase difference plates include more than two phase difference plates laminated and disposed on one side or both sides of the liquid crystal display cell with various suitable disposition conditions, so that the whiteness level of the display can be improved. In one example, they are placed so that the retardation value of each of the phase difference plates is added and a cross angle between the slow axis of the first phase difference plate and the slow axis of the nth phase difference plate is 20.degree. to 40.degree., and a further cross angle between the slow axis of the first phase difference plate and the rubbing axis of the substrate adjacent to the liquid crystal display cell is in a range from 70.degree. to 90.degree..

Abstract: Driver and receiver circuits for a differential-signal electrical interface contain comparators and resistive networks to eliminate the need for operational amplifiers, thus lowering cost and raising reliability. The preferred embodiments for the driver and receiver are optimized for use with transistor-transistor logic (TTL) signals and the International Telegraph and Telephone Consultative Committee (CCITT) 1985 Recommendation V.35, which recommendation was designed for use with wideband modems.

Abstract: A half-tone pixel having subpixels and control capacitor constituting a 100 percent optically active pixel. The subpixel design results in no reductions in the maximum pixel aperture ratio, brightness or contrast, as a pixel with no subpixels would have. Various subpixel layouts including differing numbers of subpixels and subpixel-turn-on sequences may be implemented and still result in the entire pixel being optically active.

Abstract: The inventive power supply detecting circuit includes an additional fifth, sixth, seventh and eighth MOS transistors within an output buffer H bridge circuit of a conventional type, in order to reduce the power consumption in the electric current detection circuit thereof. The fifth MOS transistor has a drain connected to a power supply terminal. Its source is connected to an electric current detecting terminal. Its gate is connected to a first internal input terminal. The sixth MOS transistor has a drain connected to the electric current detecting terminal. Its source is connected to a first output terminal. Its gate is connected to the first internal input terminal. The seventh MOS transistor has a drain connected to the power supply terminal. Its source is connected to the electric current detecting terminal. Its gate is connected to a second internal input terminal. The eighth MOS transistor has a drain connected to the electric current detecting terminal.

Abstract: Disclosed is a divide-by-m counter for generating an ouptut clock signal having a fifty percent duty cycle from a higher frequency source clock signal having m cycles for each single cycle of the output clock signal and wherein m may be an odd or even integer number, the divide-by-m counter including a modulo binary counter for counting up to a predetermined number, circuitry for presetting the modulo binary counter by another predetermined number, counter clock selector for providing a counter clock signal to the modulo binary counter which, when m is odd, will be either an non-inverted source clock or an inverted source clock based upon the occurrence of either the HIGH or LOW intervals of the output clock, and interval defining circuitry for defining the beginning of such HIGH and LOW intervals of the output clock based upon the occurrence of a ripple carry pulse from the modulo binary counter.

Abstract: The object of the present invention is to provide a phase detector comprising three D-type flip-flops, which compares the transition phase of retiming clock pulses with the phase of the center of the unit bit interval of received data, produces the compared result in digital fashion to operate irrespective of the data bit speed and in the form of a phase information that is compatible with a digital circuit.

Abstract: A circuit for presenting a multiplied impedance at in input node includes a resistor having a value desired to be multiplied at the input node connected at one end to a reference potential. A first transistor has a current path in series between the input node and the other end of the resistor. A voltage divider is connected at one end to the reference potential, and a second transistor has a current path in series between a voltage source and the other end of the voltage divider, so that the second transistor and the voltage divider form an emitter follower circuit, to provide feedback to said first transistor circuit. A current control element of the first transistor is connected to receive the divided voltage from the voltage divider, and a current control element of the second transistor being connected to the input node. The transistors can be either bipolar, enhancement FET or MOS enhancement FET type devices.

Abstract: A switching circuit for a switched power supply, and the like, which includes a field effect transistor as a power switch. The switching circuit includes a simple circuit for providing gate drive bias for the field effect transistor which forces it to share turn-off voltage with other field effect transistors connected in series with it. The switching circuit also includes a network for generating a negative gate bias for the field effect transistor to speed up switch-off of the transistor.

Abstract: A composite signal processor and single-ended noise reduction system uses a split input to the single-ended noise reduction circuit in such a manner that the audio signal from the output of the signal processor circuit is dynamically filtered in response to a control signal derived from the unaltered audio signal prior to signal processing. User selective switching is also provided to permit the signal processor and the noise reduction circuit to be used simultaneously or independently.

Abstract: A liquid crystal device comprises two electrode plates and a liquid crystal such as a ferro-electric smectic liquid crystal disposed between the electrode plates. At least one electrode plate is provided with a uniaxial orientation treatment. At least one electrode plate comprises a substrate and transparent stripe electrodes and metal electrodes each disposed along the length of and electrically connected with a transparent stripe electrode formed on a substrate. Each metal electrode is disposed along and forms a protrusion sticking out of at least one longitudinal edge of a transparent stripe electrode.

Abstract: A process for preparing a liquid crystal cell by irradiating on a transparent electrode a laser beam having a broader area than an outer shape of a conductive matter about the conductive matter, wherein the conductive matter is located between said two substrates having an alignment control film subjected to monoaxial alignment treatment.

Abstract: A liquid crystal device (10) includes at least two layers of encapsulated thermochromic, e.g., liquid crystal, material (14, 16) for providing a color response with respect to temperature, the temperature ranges of color response of the at least two liquid crystal layers being different, a mechanism (18) for distinguishing the temperature range in which the device is operational, and a support (20) for supporting the at least two liquid crystal layers and distinguishing mechanism for positioning with respect to at least part of a body. A method for making the liquid crystal device and a method for using the liquid crystal device to detect and to indicate the temperature of a body.

Abstract: A Bi-CMOS circuit according to the present invention includes a first transistor made from an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal and that supplies a first current to the base of an output transistor when the first transistor is turned on, and an active pull-down current supplying means connected to the gate electrode of the first transistor. The active pull-down current supplying means provides a second current, which is an active pull-down current, to the base of the output transistor so that the first and second currents can be supplied to the base of the output transistor.

Abstract: In an FET differential input, preferably using a quad set of devices according to the teaching of U.S. Pat. No. 3,729,660, the channel of each transistor is formed in a piecewise manner, of multiple segments. Each channel segment is associated with a corresponding drain segment (i.e., these are multi-drain devices). Each drain segment is connected in series with a thin-film resistor. The channel area associated with each drain segment can be selectively removed from the circuit by cutting the connected resistor with a laser. The device's channel area (and its effective width to length ratio, Z/L) is thereby alterable. The thin film resistors are cut as the offset is measured, until an acceptably low (effectively zero) offset is obtained. This trimming operation can be performed at room temperature, and yields not only a near zero offset voltage, but also near zero drift. CMRR, further, will be maximized. Neither operating current ratio nor drain voltage need be, or is, changed.

Abstract: A Digital Phase Comparator has a simplified logic circuit in which Nand Circuits provide UP and DOWN signals containing phase information about E and F signals.

Abstract: Relaxation effects of a uniform mode ferroelectric liquid crystal cell with obliquely evaporated alignment layers, characterized by the reduction in apparent tilt angle consequent upon removal of a switching stimulus, are eliminated by a poling treatment that typically comprises the application of a relatively low frequency (c. 500 Hz) relatively large amplitude (c. 60 volts peak-to-peak) electric potential difference across the thickness of the liquid crystal layer.

Abstract: A clock chopper/expander circuit 10 includes a reset dominant latch circuit 20 which is set by a CLOCK IN signal 12 and reset by a delayed CLOCK IN signal labelled DELAY 26, provided by an asymmetrical delay circuit 22 which delays the CLOCK IN signal T.sub.D seconds. The delay circuit 22 utilizes an adjustable bias current source 64 to bias a half memory cell 50, which charges up a node 62 according to the write time of the cell 50. A sensing circuit triggers a DELAY transition when node 62 crosses a voltage predetermined by the bias provided to a second half memory cell 52 which is also controlled by the bias current source 64. A multiplexer 24 provides disablement of the clock chopping/expanding function and an OR gate 14 facilitates easy measurement of the actual delay introduced by circuit 22.

Abstract: An LCD display system is formed by stacking two or more independently operated LCD elements. By exploiting the birefringent effect of STN nematic liquid crystals a full range of colors may be displayed. Display rows in the stacked panels are preferably interlaced to achieve high display resolution. Optics are desirably included to collimate light, illuminating the stacked elements, to reduce parallax effects and to disperse light exiting the stacked elements to permit wide angle viewing. The contrast between a pixel in the dark state and in the white state of the high resolution display system may be increased by modifying the .DELTA.nd product of the liquid crystal in the passive regions to compensate for the natural birefringence of the liquid crystal in optically aligned active regions.

Abstract: In a circuit array for setting the operating point of a first transistor. A current-inverting circuit (current mirror circuit) has a pinch resistor connected in series with the base-emitter path of another transistor within the current inverting circuit. The current inverting circuit supplies the current-inverting base current of the first transistor.