Abstract: According to this invention, the emitters of the transistors constituting a differential amplifier are biased by a constant current source. A current mirror circuit is connected to the collectors of the transistors constituting the differential amplifier. A reference potential circuit for generating a reference potential is connected to the base of one of the transistors constituting the differential amplifier, and an output current from the current mirror circuit is fed back to the base of the other transistor. Therefore, the reference potential generated from the reference potential circuit is applied to the base of the other transistor. The reference potential applied to the base of the other transistor is applied to the base of a transistor of Darlington-connected transistors which receives an input signal, and the reference potential serves as a bias power source voltage.

Abstract: A pulse control circuit generates latch signals in response to edges of externally-input pulses and generates a resetting signal after each of the latch signals is generated. A pulse position measurement counter counts reference clock signals, thereby measuring the time interval between the generation of one latch signal and the generation of the succeeding latch signal. In response to the latch signal, a latch circuit latches the time interval measured by the pulse position measurement counter as output data. A pulse detector detects that the time interval between successive latch signals is shorter than a predetermined time. It also detects that the number of latch signals which have been input is larger than a predetermined number. A data control circuit is employed in association with the pulse detector.

Abstract: A timing generator, which is simple in structure, has high linearity, and operates at high speeds, is realized by varying the equivalent input capacitance of a mirror amplifier. The mirror capacitance is electrically discharged with a constant current in the saturation region and in the linear region of the amplifier. The voltage at the inverting input terminal of the mirror amplifier is compared with a constant value to produce a delay. When the delay is produced in the linear region, where the inclination of the ramp waveform is mild, the period of the delay is accurately varied by input data. Thus, the period of the delay can be set with high accuracy, and high resolution. In the saturation region, where the inclination of the ramp waveform is steep, the voltage is compared with a constant value. Thus, the timing generator is made immune to noise, even if the delay time is lengthy.

Abstract: Disclosed is a sense amplifier employing an emitter coupled logic (ECL) circuit. A constant voltage generating circuit independent of a change or a fluctuation of a power supply voltage level is provided. Two current-mirror circuits supply constant currents to the ECL circuit based on a generated constant voltage. Since a constant current independent of the change of power supply voltage level is supplied to the ECL circuit, the ECL circuit reliably converts a small potential difference generated between I/O lines into a current signal. Accordingly, no erroneous reading operation is performed.

Abstract: A level conversion circuit includes a level converter and a buffer gate circuit. A level converter includes two pairs of P-channel MOS transistors. A first input signal is supplied to one of the pair of P-channel MOS transistors and a second input signal is supplied to one of the other pair of P-channel MOS transistors. Each of the first and second input signals are complementary ECL-level signals. The buffer gate circuit includes two BiCMOS circuits. A first output signal from one of the pairs of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in one of the BiCMOS circuits. A second output signal from the other pair of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in the other BiCMOS circuit. The first input signal is supplied directly to a gate of a P-channel MOS transistor provided in one the BiCMOS circuits.

Abstract: Ferroelectric liquid crystal screen with opacified electrodes in the non-switchable area of the screen and processes for obtaining spacers and treating said screen.On each part of each row or column electrode of the screen, facing a gap separating two column or row electrodes is arranged an element (40,50) preventing the passage through the screen of light reaching the latter in the direction of the element. The elements located on the row electrodes (32) or those located on the column electrodes (34) also permit the spacing, without electrical connection, of the screen plates and the localization of the zigzag defects which the liquid crystal may have, in or in the vicinity of the non-switchable area of the screen. The screen is appropriately heated and an alternating voltage is applied between the electrodes in order to localize the zigzag defects of the liquid crystal in the vicinity of the spacing elements.

Abstract: A circuit for sampling a digital input signal utilizing an asynchronous strobe signal and a method for such synchronization are disclosed. The circuit includes an input storage element, such as a latch, which stores the input signal upon receipt of a strobe signal. There is a possibility that the input storage element will become temporarily metastable, with the output of the element being indeterminate, should the digital input signal change levels at substantially the time that the strobe signal is received. The subject synchronization circuit includes circuitry which senses when the input storage element is metastable and gating circuitry which produces a synchronized signal after receipt of the strobe signal, provided the input storage element is not metastable. The synchronized signal can then be used to clock the stored input signal.

Abstract: A data link controller receiver is disclosed that includes a series of shift registers and a bit counter that counts the number of received bits. When an end of frame character is received, the value in the bit counter which represents the bit residue is supplied to a bit adjustment counter. The bit adjustment counter is employed to control the operation of the shift register containing the bit residue during a byte adjust operation, in a manner which enables the shift register containing the bit residue to be clocked until the value in the bit adjustment counter is indicative of the number of bits in a defined byte. Accordingly, the bit residue is serially shifted until the least significant bit of the shift register is filled. In addition, a mechanism is provided for loading zeros into the shift register during the byte adjust operation.

Abstract: A liquid crystal display comprising a liquid crystal element, at least two birefringent films and a pair of polarizing sheets so arranged that said element and said films are held therebetween, said liquid crystal element comprising a cell composed of two sheets of substrates and a twisted nematic liquid crystal, each substrate being provided with an electrode on one surface thereof, said substrates being arranged so that the electrodes are opposed to each other and said twisted nematic liquid crystal being held between said electrodes, characterized in that said birefringent films are composed of at least one uniaxially stretched film of a polymer having a positive intrinsic birefringence and light transmission properties and at least one uniaxially stretched film of a polymer having a negative intrinsic birefringence and light transmission properties.

Abstract: A display having (a) a first electrode; (b) a second electrode; (c) a display medium positioned between the first and second electrodes, which display medium is switchable between a first state in which incident light is at least one of scattered and absorbed and a second state in which the amount of such scattering and/or absorption is reduced; and (d) scattering centers disposed in front of the second electrode for scattering incident light with a scattering half angle of between about 2 and about 40 degrees when the display medium is in its second state, while permitting at least 10% of the incident light to be transmitted.

Abstract: An amplitude variable pulse generator is provided with two voltage supply sources. The first voltage source supplies a variable voltage which determines the amplitude of the output pulse. The second voltage source is a fixed or constant voltage source which provides a voltage lower in value than the first voltage. The second voltage source quickly pulls up a voltage between a drain and a source of a switching MOSFET, which generates the output pulse, by providing a charging voltage for an output capacitance of the MOSFET. By doing so, the output capacitance of the MOSFET is quickly reduced, and the trailing edge of the output pulse is not rounded even when the variable voltage is low. As a result, the waveform of the output pulse is not rounded for a very small amplitude pulse. Resolution of a supersonic wave device especially a supersonic diagnostic device is thereby improved.

Abstract: A controlled slew rate buffer is disclosed which comprises a driver receiving voltage along a voltage supply line and includes feedback apparatus which senses the noise level along the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold. The driver comprises at least one of (1) first and second VSS voltage sources and (2) first and second VDD voltage sources.

Abstract: An improved CMOS voltage level translator circuit having an interface stage, an intermediate stage and an output stage is presented. The inventive circuit is characterized by low crossover current in the output and intermediate stages while maintaining minimal delay response when translating a lower potential signal into a higher potential signal. The improved translator circuit may be used in applications such as during EEPROM programming where control signals with normal voltage TTL voltage swing of V.sub.CC and V.sub.SS need to interface with the EEPROM row decoders which require a much higher voltage swing of V.sub.CC ' (>V hd CC) and V.sub.SS.

Abstract: In an input buffer, logic level discrimination is provided by a first circuit which provides a first current to the output so that the output voltage is a hysteresis function of the input volt. To improve transient response without increasing power consumption, a second circuit is used to provide a second current to the output in support of the first current during transient periods of the input signal.

Abstract: A display having a first electrode means; a second electrode means; and a display medium positioned between the first and second electrode means, which display medium contains a pleochroic dye, is switchable between a first state in which incident light is substantially absorbed by the pleochroic dye and a second state in which the amount of such absorption is substantially reduced, and is capable of scattering incident light with a scattering half angle between about 5 and about 40 degrees when the display medium is in its second state, while permitting at least 10% of the incident light to be transmitted. The absolute difference between the ordinary index of refraction of the liquid crystal and the refractive index of the containment medium is 0.10 to 0.20.

Abstract: A shift register includes transistors having conduction paths serially connected at a node and between an input terminal receiving a constant voltage and a clocked terminal receiving a clocked voltage of a first phase. The control electrode of one of the transistors receives a clocked voltage of a second phase and the control electrode of the other transistor receives an input signal. An inverter is arranged between the node and the output terminal.

Abstract: A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount.

Abstract: A dot matrix type liquid crystal display device having two groups of mutually crossing parallel electrodes sandwiching a liquid crystal layer, the electrodes of one group having an aperture at each electrode crossing area along the direction of and centrally at the electrode of the other group. The electric field at the aperture portion is constantly slanted to a predetermined direction to present uniform and wide stable display areas.

Abstract: A liquid crystal display device includes a first twisted nematic liquid crystal cell and an optically anisotropic material sandwiched between two polarizers. A second twisted nematic liquid crystal cell or polymer film serves as the optically anisotropic material. The optically anisotropic material may be disposed on one or both sides of the first twisted nematic liquid crystal. The optically anisotropic material compensates for the elliptical polarization of the light passing through the liquid crystal cell so that the device transmits white light in the OFF state and appears black in the ON state.

Abstract: A liquid crystal element includes a liquid crystal having a molecular orientation varying according to an applied voltage, first upper and lower electrodes which are opposed in plane to each other and between which the liquid crystal is interposed, and second upper and lower electrodes which are not opposed in plane to each other and between which the liquid crystal is interposed. Phasic variations of the liquid crystal element are obtained by means of a first electric field which is impressed on the liquid crystal by applying a first voltage between the first upper and lower electrodes and a second electric filed which is generated by applying between the second upper and lower electrodes a second voltage which differs from the first voltage.