Abstract: A system for enhancing the error correction capability of an error correction code (“ECC”) during error recovery operations accumulates, for respective bits, counts of the number of times the bits are detected as 1s in multiple re-reads of a data signal. The system then determines, based on the associated count, if a reconstructed bit should be considered a 1 or 0, or neither, that is, if the reconstructed bit should be considered erroneous, by comparing the count to a majority detection threshold and then to either an upper or a lower predetermined threshold that corresponds to the confidence with which the bit is reconstructed as a either a 1 or a 0. If the confidence is sufficiently low, that is, if the count falls below the upper threshold or above the lower threshold, the reconstructed bit is flagged as erroneous.

Abstract: A method of correcting corrupted primitives transmitted between a serial advanced technology attachment (SATA) host and a SATA device includes detecting the presence of a corrupted primitive; analyzing a current state, a previously transmitted primitive, or a previously received primitive; selecting at least one candidate primitive according to at least one of the current state, the previously transmitted primitive, and the previously received primitive; predicting the identity of the corrupted primitive according to at least one candidate primitive and the corrupted primitive; and replacing the corrupted primitive with the predicted primitive.

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A transmitting device applies an outer code, which may include, for example, a block code, an exclusive OR (XOR) code, or a repetition code, to one or more packets prior to adaptation of the packets for transmission over the physical (PHY) layer of the communications system, wherein the PHY layer adaptation may include FEC encoding of individual packets. The outer coded packets are then separately transmitted over a channel of the communications system. A receiving device receives the outer coded packets, performs PHY level demodulation and optional FEC decoding of the packets, and then applies outer code decoding to the outer coded packets in order to restore packets that were erased during transmission due to burst noise or other impairments on the channel.

Abstract: LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.

Abstract: A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).

Abstract: Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.

Abstract: Methods, apparatus, and computer program products are disclosed for communicating with error checking to a device capable of operating according to an address prefix serial bus protocol that includes identifying whether the device supports error checking, and if the device supports error checking: setting the device in an error checking mode and sending a message with error checking data to the device. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include performing an error checking operation on the message to obtain error checking data. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include retrieving the device's error checking capability from a device table.

Abstract: A data compression method and system is disclosed. In one embodiment, the data compression method includes receiving a data packet. Also, the method includes compressing the data packet using a confirmed compression history, wherein the confirmed compression history includes previously acknowledged data packets. Further, the method includes sending a compressed data packet to a downstream device. Moreover, the method includes detecting a delivery acknowledgement associated with the compressed data packet. Continuing, the method includes updating the confirmed compression history by incorporating the data packet information into the confirmed compression history based upon receipt of the delivery acknowledgement.

Abstract: This invention generally relates to methods, apparatus and computer program code for decoding signals, and more particularly to trellis-based decoding using a variant of a BCJR procedure.

Abstract: A method for transferring and correcting communication data is provided. The communication data include data frames, wherein each data frame includes data packets logically arranged in a number of rows and columns. Each data frame also includes error correction packets associated with the data packets. The error correction packets are generated according to an error correction scheme based on the number of rows and columns. The data frames are transmitted and received. The error correction packets are processed to correct errors in the data packets. Information regarding the errors in the data packets is generated. This information is processed to alter at least one of the number of rows and the number of columns.

Abstract: Circuits and methods provide the concurrent calculation of CRC bits for messages from different channels, where one part of a message is received at a time. Context buffers store certain state variables of the CRC calculation for each channel. The context buffers output data in a synchronized manner with the input data so that the proper calculations are done and the proper data is available at the appropriate times.

Abstract: A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is configured to overwrite at least a portion of externally input write data on data read out from a memory cell and corrected by the error correction circuit, and write the overwritten data in the memory cell. The output circuit is configured to output the overwritten data outside a chip. The second write circuit is configured to reoverwrite at least a portion of write data which is externally input at a different time on the overwritten data, encode the reoverwritten data, and write the encoded data in the memory cell.

Abstract: Techniques are described for use by an implantable medical device equipped to use trim values, which allow the device to continue to use trim values despite certain memory errors such as parity errors. Briefly, optimal trim values are stored within RAM. Nominal trim values are stored within ROM. Device functions are then performed using the trim values stored within RAM. If an error is detected indicative of possible corruption of RAM, then the trim values from ROM are loaded into RAM to enable continued operation of the device using the nominal trim values despite the error. In a preferred implementation, the optimized trim values are initially stored at two separate locations within RAM. A procedure is described herein for allowing the device to continue to use the optimized trim values following a device reset if no parity error is detected. If a parity error occurred, the device instead uses the nominal trim values from ROM.

Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

Abstract: Methods and systems for improving repairing efficiency in non-volatile memory. Repairing data may be read from an information array associated with the non-volatile memory. The repairing data is generally read to a volatile latch associated with the non-volatile memory. An error correction coding circuit (ECC) circuit can be enabled during reading of the repairing data for identifying and repairing defective columns or rows associated with the non-volatile memory, despite errors in the repairing data read out.

Abstract: A circuit to reduce noise spikes on the power and ground rails of a chip when switching over an input-output bus, the circuit comprising an encoder to encode a word before transmission over the input-output bus so that the difference in the number of 1 bits and the number of 0 bits in the encoded word is upper bounded, where the upper bound is less than the length of the original word before encoding. An embodiment circuit to implement this encoding comprises partitioning the word into a plurality of smaller words. An embodiment circuit further comprises a number of stages, where in the first stage, there are a plurality of encoders to encode in pair-wise fashion the smaller words. Additional stages also comprise a plurality of encoders, each encoder performing a pair-wise encoding of words outputted by a previous stage. Other embodiments are described and claimed.

Abstract: Provided is an apparatus and method for receiving a signal in communication system. The apparatus and method includes generating a particular log-likelihood ratio (LLR) value by demapping an input signal according to a particular demapping scheme among a plurality of demapping schemes; performing a control operation of buffering the particular LLR value in a particular LLR sub-buffer for buffering an LLR value generated according to the particular demapping scheme among the plurality of LLR sub-buffers for buffering an LLR value generated according to each of the plurality of demapping schemes; and performing a control operation of reading an LLR value buffered in an LLR buffer including the plurality of LLR sub-buffers.

Abstract: A technique to perform carry-less multiplication and bit reflection operations. More specifically, embodiments of the invention include an instruction to perform carry-less multiplication and an instruction to perform a bit reflection operation.

Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

Abstract: A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.