Abstract: Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.

Abstract: An organic light emitting diode (OLED) display includes a display substrate assembly including an organic light emitting structure, an encapsulation substrate assembly disposed facing the display substrate assembly, a sealant disposed between the display substrate assembly and the encapsulation substrate assembly to seal the display substrate assembly and the encapsulation substrate assembly with each other, and a substrate deformation protection body disposed between the sealant and the organic light emitting structure.

Abstract: A semiconductor device includes a semiconductor chip having a surface provided with connecting electrodes, a stacked structure made up of alternately stacked dielectric and wiring layers and provided on the surface of the semiconductor chip, a passive element provided in the stacked structure and electrically connected to the wiring layers; and external electrodes for external electrical connection provided on the stacked structure and electrically connected to the connecting electrodes via the wiring layers. The passive element has at least one layer selected from a group consisting of a capacitor dielectric layer, a resistor layer and a conductor layer that are formed by spraying an aerosol particulate material.

Abstract: In a lamination type semiconductor device, in the case where a power source plane is wrapped by a closed area to prevent the needless radiation from being leaked to the outside of the semiconductor package, a planar conductor for shield having an area intersecting with the respective layers is required. However, in a device for manufacturing the lamination type semiconductor device, a process for manufacturing the above-mentioned conductor cannot be realized ordinarily. In order to make the process possible, it is required to modify or replace a manufacturing apparatus of the semiconductor device, and accordingly a manufacturing cost will be considerably increased. In the present invention, a guard ring is arranged in an surrounding area of a power source plane. The guard ring is connected to a GND plane of another layer through a via. Consequently, the RF radiation occurs between the power source plane and the guard ring.

Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Abstract: A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall.

Abstract: A semiconductor storage device including a semiconductor substrate including an upper surface having a plurality of trenches formed into the upper surface; a plurality of element isolation insulating films filled in each of the trenches so as to protrude upward from the upper surface of the semiconductor substrate, the element isolation insulating films containing an oxide material; a tunnel insulating film formed on the semiconductor substrate situated between the element isolation insulating films; a charge storing layer comprising a first nitride film and being formed on the tunnel insulating film; a block film formed across an upper surface of the charge storing layer and an upper surface of the element isolation insulating film to prevent charge transfer; a gate electrode formed on the block film; and a barrier layer containing a second nitride film formed between the element isolation insulating film and the block film.

Abstract: A semiconductor device according to the invention includes n-type semiconductor substrate 1; trenches 15 formed in the surface portion of semiconductor substrate 1; a protruding semiconductor region between trenches 15; p-type base layer 2 in the protruding semiconductor region, p-type base layer 2 being positioned as deep as or shallower than trench 15; an n++-type emitter region or a source region in the surface portion of p-type base layer 2; gate insulator film 4a on the first side wall of the protruding semiconductor region; and gate electrode 6 on gate insulator film 4a. Trench 15 is from 0.5 ?m to 3.0 ?m deep and the short side of trench 15 is 1.0 ?m or longer. The short side of the protruding semiconductor region is from 0.5 ?m to 3.0 ?m long. Gate electrode 6 contains electrically conductive polycrystalline silicon as its main component. Gate electrode 6 is from 0.2 ?m to 1.0 ?m thick.

Abstract: A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

Abstract: Interfused nanocrystals including two or more materials, further including an alloy layer formed of the two or more materials. In addition, a method of preparing the interfused nanocrystals. In the interfused nanocrystals, the alloy layer may be present at the interface between the two or more nanocrystals, thus increasing the material stability. A material having excellent quantum efficiency in the blue light range may be synthesized.

Abstract: Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Abstract: An encapsulation of a sensitive component structure on a semiconductor substrate with a film covering the component structure is disclosed. A cavity for the component structure is provided in the film. A MEMS and a method for encapsulating a sensitive component structure is also disclosed.

Abstract: An organic electroluminescence device and a method of manufacturing the same are provided. The organic electroluminescence device is suitable for being configured on a substrate. The organic electroluminescence device includes a first electrode, a first doped carrier transporting layer, a light-emitting layer, a second doped carrier transporting layer, and a second electrode. The first electrode is configured on the substrate. The first doped carrier transporting layer is configured on the first electrode. The light-emitting layer is configured on the first doped carrier transporting layer. The second doped carrier transporting layer is configured on the light-emitting layer and has a first surface in contact with the light-emitting layer and a second surface opposite to the first surface. The first surface is substantially a planar surface, and the second surface is a rough surface having a plurality of micro-protrusions. The second electrode is configured on the second surface.

Abstract: A semiconductor light emitting element of the present invention comprises: a zinc oxide (ZnO) single crystal substrate 12 with a substrate surface of a plane orientation insusceptible to a piezo electric field; a Lattice-matched layer 13 formed on the substrate surface to be lattice-matched with the ZnO single crystal substrate 12; an active layer 15 of indium gallium nitride (InxGa1-xN, 0<x<1); two of cladding layers 14 and 16 to be lattice-matched with the active layer 15 and/or the Lattice-matched layer 13.

Abstract: Complementary MOS (CMOS) integrated circuits include MOS transistors, resistors and bipolar transistors formed on a common substrate. An emitter region of a bipolar transistor is implanted with a first dopant in an implantation process that implants source/drain regions of an MOS transistor, and is also implanted with a second dopant of same conductivity type in another implantation process that implants a body region of a resistor. The first and second dopants may optionally be the same dopant. The source/drain regions are implanted with the resistor body region covered by a first patterned mask; and the resistor body region is implanted with the MOS transistor source/drain regions covered by a second patterned mask. The implantations of the MOS transistor source/drain regions and of the resistor body region the source/drain regions can occur in any order, with the emitter region implanted during both implantations.

Abstract: An embodiment of the invention provides a chip package, which includes a substrate having an upper surface and a lower surface, a chip disposed in or on the substrate, a pad disposed in or on the substrate and electrically connected to the chip, a hole extending from the lower surface toward the upper surface, exposing the pad, wherein a lower opening of the hole near the lower surface has a width that is shorter than that of an upper opening of the hole near the upper surface, an insulating layer located overlying a sidewall of the hole, and a conducting layer located overlying the insulating layer and electrically connected to the pad.

Abstract: A light emitting device including a light emitting structure having a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a first electrode on the light emitting structure; and a photon escape layer on the light emitting structure. Further, the photon escape layer has a refractive index that is between a refractive index of the light emitting structure and a refractive index of an encapsulating material with respect to the light emitting structure such that an escape probability for photons emitted by the light emitting structure is increased.

Abstract: A semiconductor subassembly is provided for use in a switching module of an inverter circuit for a high power, alternating current motor application. The semiconductor subassembly includes a wafer having first and second opposed metallized faces; a semiconductor switching device electrically coupled to the first metallized face of the wafer and having at least one electrode region; and an interconnect bonded to the semiconductor switching device. The interconnect includes a first metal layer bonded to the at least one electrode region of the semiconductor switching device, a ceramic layer bonded to the first metal layer, the ceramic layer defining a via for accessing the first metal layer, a second metal layer bonded to the ceramic layer, and a conducting substance disposed in the via of the ceramic layer to electrically couple the first metal layer to the second metal layer.

Abstract: A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via.

Abstract: A memory circuit includes multiple memory chips configured to store data and disposed in at least one stack. The memory circuit includes multiple ports configured to receive and transmit control signals and data to and from the memory chips and to supply energy to the memory circuit. The memory circuit includes a housing accommodating the multiple memory chips and the multiple ports.