Abstract: There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

Abstract: Systems and methods for increasing peak ion energy with a low angular spread of ions are described. In one of the systems, multiple radio frequency (RF) generators that are coupled to an upper electrode associated with a plasma chamber are operated in two different states, such as two different frequency levels, for pulsing of the RF generators. The pulsing of the RF generators facilitates a transfer of ion energy during one of the states to another one of the states for increasing ion energy during the other state to further increase a rate of processing a substrate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.

Abstract: A semiconductor device includes a stacked body 100, first insulating layers 45, a second insulating layer 46 and columnar portions CL. The stacked body 100 includes electrode layers 41 stacked with an insulating body interposed along a Z-direction. The first insulating layers 45 extend in an X-direction and are provided in the stacked body 100 from an upper end thereof to a lower end thereof. The second insulating layer extends in the X-direction and is provided in the stacked body 100 from the upper end to partway through the stacked body 100 between one of the first insulating layers 45 and another one of the first insulating layers 45. The columnar portion CL has a bowed configuration. The second insulating layer 46 is provided in a region B including a location of a maximum inner diameter Dm of the columnar portion CL.

Abstract: A semiconductor light emitting element having: a semiconductor laminated body; a full surface electrode containing an Ag provided on an upper surface of the p-type semiconductor layer; a cover electrode that covers a surface of the full surface electrode, is provided to contact on the upper surface of the p-type semiconductor layer at an outer edge of the full surface electrode, and is made of an Al-based metal material; a p-side electrode that is provided on a portion of a surface of the cover electrode; a metal oxide film that covers other surfaces of the cover electrode and contains an oxide of a metal material forming the cover electrode; and an insulation film that is made of an oxide and covers a surface of the metal oxide film, is provided.

Abstract: A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.

Abstract: A light-emitting device includes a light-emitting element, a light pervious layer, an electrode defining layer, a first soldering pad and a second soldering pad. The light-emitting element has an upper surface, a bottom surface, and a lateral surface arranged between the upper surface and the bottom surface. The light pervious layer covers the upper surface and the lateral surface. The electrode defining layer covers a part of the light pervious layer. The first soldering pad and the second soldering pad are surrounded by the electrode defining layer. A gap is located between the first soldering pad and the second soldering pad while the gap remains substantially constant.

Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

Abstract: A light source comprises light emitting diodes (LED) (1) with a monocrystal (2), covered by a cap (3) of a transparent material at one side and fitted with an anode contact element (4) to supply and a cathode contact element (5) to lead away direct current at the other side. The LED's arranged in a row are connected with their anode contact elements to one thermally and electrically conductive cooling plate (43, 45) and with their cathode contact elements (5) to another cooling plate (53, 55). These mutually insulated cooling plates are arranged with their lateral sides next to each other and on the surfaces averted from the LED's they are fitted with cooling elements for transfer of heat to cooling media. The cooling elements may comprise sets of cooling fins (44, 54; 46, 56) arranged on the sides of the cooling plates averted from the LED's.

Abstract: A method for fabricating calcite channels in a nanofluidic device is described. A photoresist is coated on a substrate, and a portion of the photoresist is then exposed to a beam of electrons in a channel pattern. The exposed portion of the photoresist is developed to form a channel pattern, and calcite is deposited in the channel pattern using a calcite precursor gas. The deposited calcite includes at least one side having a length in a range of approximately 50 to 100 nanometers. The photoresist remaining after developing the exposed portion of the photoresist is removed.

Abstract: The present application relates to an organic light emitting device.

Abstract: A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.

Abstract: Image sensors, and electronic devices including the image sensors, include a first photoelectronic device including at least one of a blue photoelectronic device sensing light in a blue wavelength region, a red photoelectronic device sensing light in a red wavelength region, and a green photoelectronic device sensing light in a green wavelength region, and a second photoelectronic device stacked on one side of the first photoelectronic device without being interposed by a color filter, wherein the second photoelectronic device senses light in an infrared region.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.

Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.

Abstract: A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a first impurity region in the active region, an anti-fuse gate electrode on the semiconductor substrate and extending across the first impurity region, an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region, a selection gate electrode on the semiconductor substrate and extending across the active region, a selection gate dielectric layer between the selection gate electrode and the active region, and a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode. The first and second impurity regions have impurities of a second conductivity type. The first impurity region has an impurity concentration less than the impurity concentration of the second impurity region.

Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

Abstract: A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

Abstract: An optical device includes a substrate, a semiconductor chip, a resin member, and a transparent plate. The semiconductor chip is provided on the substrate, and an optically functional layer is formed in a part of a top portion of the semiconductor chip. The resin member is provided on the substrate with a top surface and an inner side surface, and has a frame shape surrounding the optically functional layer. The resin member is integrally formed from a resin material, and includes a recessed portion provided at the intersection of the top surface and the inner side surface. The transparent plate is disposed in the recessed portion. The semiconductor chip, the resin member, and the transparent plate are arranged to define airspace.