Patents Examined by Suberr L Chi
  • Pigmented and scattering particles in side coating materials for LED applications
    Patent number: 11302849
    Abstract: Phosphor-converted LED side reflectors disclosed herein comprise pigments that are photochemically stable under illumination by light from the pcLED. The pigments absorb light in at least a portion of the spectrum of light emitted by the first phosphor converted LED. The side reflector may also comprise light scattering particles and/or air voids. The pigments, light scattering particles and/or air voids may be homogeneously distributed in the reflector. Alternatively the side reflector may be layered, with the pigments, light scattering particles and/or air voids inhomogeneously distributed in the reflector. The side reflector may comprise phosphor particles.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 12, 2022
    Assignee: Lumileds LLC
    Inventors: Grigoriy Basin, Kentaro Shimizu, Brendan Moran, Emma Dohner, Noad Shapiro, Marcel Bohmer
  • Circuit board and light emitting device including circuit board
    Patent number: 11304291
    Abstract: A circuit board according to the present disclosure includes a substrate, a conductor layer arranged on the substrate, a reflective layer arranged on the conductor layer, and a silicone-resin layer arranged on the substrate. The silicone-resin layer is in contact with the conductor layer and the reflective layer. The silicone-resin layer contains equal to or more than 45% by mass of a plurality of fillers. A first filler whose aspect ratio is larger than 5 occupies equal to or more than 5% of 100% of a total number of the fillers.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 12, 2022
    Assignee: KYOCERA CORPORATION
    Inventor: Yuichi Abe
  • Optical device package
    Patent number: 11302682
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yueh Tsai, Meng-Jen Wang, Yu-Fang Tsai, Meng-Jung Chuang
  • Interconnection structure and sensor package
    Patent number: 11296025
    Abstract: A sensor package includes a carrier, a sensor, an interconnection structure, a conductor and a housing. The sensor is disposed on the carrier. The interconnection structure is disposed on the carrier and surrounds the sensor. The interconnection structure has a first surface facing away from the carrier. The conductor is disposed on the first carrier. The conductor having a first portion covered by the interconnection structure and a second portion exposed from the first surface of the interconnection structure. The housing is disposed on the carrier and surrounds the interconnection structure.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsun-Wei Chan, Shih-Chieh Tang
  • Vertical 1T-1C DRAM array
    Patent number: 11289490
    Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Gilbert Dewey, Abhishek A. Sharma
  • Solid-state imaging device and electronic apparatus
    Patent number: 11289525
    Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 29, 2022
    Assignee: Sony Corporation
    Inventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
  • Dynamic logic built with stacked transistors sharing a common gate
    Patent number: 11282861
    Abstract: A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Rishabh Mehandru
  • Edge incident type semiconductor light receiving device
    Patent number: 11276791
    Abstract: In an edge incident type semiconductor light receiving device that reflects light incident parallel to the main surface of the semiconductor substrate opaque to the incident light to the light receiving section on the main surface side, a light guide section is formed to expose the light receiving section along the light incident direction from the light incident side end of the semiconductor substrate, and in order to guide the light incident on the light guide section to the light receiving section, a light reflection section having a given crossing angle with the main surface is provided at the end of the light guide section in the light incident direction.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: March 15, 2022
    Assignee: KYOTO SEMICONDUCTOR CO., LTD.
    Inventors: Takatomo Isomura, Etsuji Omura
  • Source/drain structure with barrier in FinFET device and method for forming the same
    Patent number: 11271111
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain feature in the substrate, protruding from the substrate, and on a sidewall surface of the gate structure. The semiconductor device structure also includes an insulating barrier structure in the substrate and partially covering the bottom and sidewalls of the source/drain feature.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Chun Kuan, I-Chih Chen, Chih-Mu Huang, Fu-Tsun Tsai, Sheng-Lin Hsieh, Kuan-Jung Chen
  • Display substrate comprising low-temperature polycrystalline oxide
    Patent number: 11271052
    Abstract: The present disclosure provides a display substrate including a display area and a fingerprint recognition area. The display area includes a low-temperature polycrystalline oxide structure, an organic light-emitting layer, a cathode layer, and an anode layer that are sequentially stacked. The fingerprint recognition area includes an under-screen fingerprint recognition structure. The low-temperature polycrystalline oxide structure and the under-screen fingerprint recognition structure are disposed on a same layer. The under-screen fingerprint recognition structure includes the cathode layer and the organic light-emitting layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 8, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Hong Gao, Mugyeom Kim
  • Display device and method for manufacturing same
    Patent number: 11264584
    Abstract: A film thickness securing region of a green island-shaped hole transport layer in a display device is located at the inside of a green pixel light-emitting region in a direction in which a red pixel and a green pixel are adjacent to each other, and part of a shadow region of a red island-shaped hole transport layer and part of a shadow region of the green island-shaped hole transport layer overlaps each other within the green pixel light-emitting region.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 1, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masao Nishiguchi
  • Display panel, display device and method for manufacturing display panel
    Patent number: 11264551
    Abstract: The present disclosure relates to display panel, display device and method for manufacturing display panel.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 1, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiangdan Dong, Youngyik Ko, Ming Hu
  • Semiconductor device including dummy gate patterns and manufacturing method thereof
    Patent number: 11264482
    Abstract: A semiconductor device may include: a dummy gate structure including a first gate pattern in which dummy gate lines extending in one direction are connected to each other on a substrate, and a second gate pattern in which dummy gate lines extending in the one direction are connected to each other on the same line with the first gate pattern; and a third gate pattern extending in parallel with the dummy gate structure on one side of the dummy gate structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghyun Kim, Inhyun Song, Yeongmin Jeon, Sejin Park, Juyun Park, Jonghoon Baek, Taeyeon Shin, Sooyeon Jeong
  • Light-receiving element and method for manufacturing element
    Patent number: 11264519
    Abstract: A light receiving element includes a first substrate, a photodiode formed on a main surface of the first substrate, and a second substrate constituted by a semiconductor and adhered to a rear surface side of the first substrate by an adhesive layer formed from a resin adhesive. A light receiving element according to an embodiment includes a lens that is formed on the side of an adhesion surface of the second substrate, has a convex surface, and is disposed in a light receiving region of the photodiode. The light receiving side of the photodiode is oriented toward the side of the first substrate. The lens is disposed so that the convex surface thereof is oriented toward the side of a light receiving surface of the photodiode.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 1, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yoshiho Maeda, Fumito Nakajima, Yoshifumi Muramoto, Atsushi Kanda, Kimikazu Sano
  • Magnetoresistive random access memory device and method for fabricating the same
    Patent number: 11258005
    Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Ting-An Chien
  • Fully self-aligned cross grid vertical memory array
    Patent number: 11251227
    Abstract: A programmable array including a plurality of cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, the transistor including a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region and includes a width dimension equivalent to a width dimension of the body of the transistor. A method of forming an integrated circuit including forming bodies in a plurality rows on a substrate, each of the bodies including a programmable element and a first diffusion region, a second diffusion region and a channel of a transistor; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material; and replacing the masking material with an address line material.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros
  • Electric component with sensitive component structures and method for producing an electric component with sensitive component structures
    Patent number: 11245977
    Abstract: The invention relates to a simple to produce electric component for chips with sensitive component structures. Said component comprises a connection structure and a switching structure on the underside of the chip and a support substrate with at least one polymer layer.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 8, 2022
    Assignee: Snaptrack, Inc.
    Inventors: Christian Bauer, Hans Krüger, Jürgen Portmann, Alois Stelzl, Wolfgang Pahl
  • Light emitting diode constructions and methods for making the same
    Patent number: 11245058
    Abstract: Light emitting diode (LED) constructions comprise an LED having a pair of electrical contacts along a bottom surface. A lens is disposed over the LED and covers a portion of the LED bottom surface. A pair of electrical terminals is connected with respective LED contacts, are sized larger than the contacts, and connect with the lens material along the LED bottom surface. A wavelength converting material may be interposed between the LED and the lens. LED constructions may comprise a number of LEDs, where the light emitted by each LED differs from one another by about 2.5 nm or less. LED constructions are made by attaching 2 or more LEDs to a common wafer by adhesive layer, forming a lens on a wafer level over each LED to provide a rigid structure, removing the common wafer, forming the electrical contacts on a wafer level, and then separating the LEDs.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 8, 2022
    Assignee: Bridgelux, Inc.
    Inventors: Vladimir A. Odnoblyudov, R. Scott West
  • Asymmetric FET for FDSOI devices
    Patent number: 11245032
    Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 8, 2022
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Ignasi Cortes, Alban Zaka, Tom Herrmann, El Mehdi Bazizi, Richard Francis Taylor, III
  • Photoelectric conversion device, substrate, and system with semiconductor regions
    Patent number: 11239380
    Abstract: Photoelectric conversion device includes semiconductor chip including first semiconductor region, second semiconductor region arranged on the first semiconductor region, and third semiconductor region arranged on the second semiconductor region. Chip end face of the semiconductor chip is formed by the first semiconductor region, the second semiconductor region and the third semiconductor region. The first semiconductor region is of first conductivity type and the second semiconductor region is of second conductivity type. The third semiconductor region includes photoelectric conversion region, readout circuit region, and peripheral region. The peripheral region includes isolation region and outer periphery region arranged between the chip end face and the isolation region. The isolation region is of the second conductivity type and the outer periphery region is of the first conductivity type.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 1, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuuichirou Hatano, Takahiro Shirai