Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

Abstract: A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.

Abstract: A heterojunction bipolar transistor, comprising: a substrate, having a first surface and an opposite second surface; a sub-emitter layer arranged on the first surface; a compound emitter layer arranged on the sub-emitter layer, making the sub-emitter layer and the compound emitter layer forms an emitter layer; a base layer arranged on the compound emitter layer; a collector ledge layer arranged on the base layer; a collector layer arranged on the collector ledge layer; a lateral oxidation region arranged on the compound emitter layer forming a current blocking region, and the outer region of the compound emitter layer surrounds inner region, so that the inner region of the compound emitter layer forms a current aperture.

Abstract: A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a gate trench portion extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the gate trench portion in an array direction orthogonal to the extending direction; a first-conductivity-type accumulation region provided above the drift region and in contact with the gate trench portion, and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region and in contact with the gate trench portion; and a second-conductivity-type floating region provided below the accumulation region and in contact with the gate trench portion, and provided in a part of the mesa portion in the array direction.

Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.

Abstract: The disclosure provides a heterojunction bipolar transistor and a preparation method thereof. Since an emitter region has the same physical structure as a base region, and improves frequency characteristics of the device; Simultaneously with biaxial strain, uniaxial strain is introduced. Carrier transmission time in the collector region will be effectively reduced. By this structure, the width of the effective collector region is reduced, the collector junction capacitance is reduced, and the frequency characteristics of the device are further improved; an appropriate choice of the thickness of the Si cap layer can effectively reduce the accumulation of carriers at an interface and increase the gain of the device; at the same time, the preparation method of the bipolar transistor is completely compatible with a 90-nanometer CMOS process, which effectively reduces the development and manufacturing cost of the device.

Abstract: Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a first layer having a first type of dopant, a second layer forming a region with at least ten times lower concentration of dopants compared to the adjacent layers, and a third layer having a second type of dopant that is opposite to the first type of dopant. The first layer of a second DSRD is positioned on top of the third layer of first DSRD. The first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.

Abstract: A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.

Abstract: This disclosure relates to a semiconductor device and corresponding method of manufacturing the semiconductor device. The semiconductor device includes a MOS transistor device die and a SiGe diode. The SiGe diode is integrally arranged on the MOS transistor device die, so that the SiGe diode is electrically connected between a source connection and drain connection of the MOS transistor device die.

Abstract: The present disclosure provides a method for manufacturing a thin film transistor and a thin film transistor, which includes providing a substrate; forming an active layer on the substrate and patterning the active layer, the active layer is made of cubic boron nitride; and forming a first insulating layer, a gate electrode metal layer, a second insulating layer, a source and drain metal layer and a flat layer on the active layer successively. the method for manufacturing a thin film transistor and the thin film transistor of the present disclosure employ cubic boron nitride instead of polysilicon as active layer materials, CVD process is directly applied to form the active layer with cubic boron nitride.

Abstract: A semiconductor device including one or more transistors is disclosed. The semiconductor device includes a first active region disposed over a well region of a substrate, a plurality of dummy active regions disposed around the first active region, and a gate disposed to traverse the first active region, wherein a portion of the gate is disposed to overlap with at least one of the plurality of dummy active regions and is electrically coupled to the at least one of the plurality of dummy active regions.

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. For example, a method for forming a 3D memory device is provided. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a substrate. A staircase structure is formed on at least one side of the dielectric stack. Dummy channel holes and dummy source holes extending vertically through the staircase structure are formed. A subset of the dummy channel holes is surrounded by the dummy source holes. A dummy channel structure is formed in each dummy channel hole, and interleaved conductive layers and dielectric layers are formed in the staircase structure by replacing, through the dummy source holes, the sacrificial layers in the staircase structure with the conductive layers. A spacer is formed along a sidewall of each dummy source hole to cover the conductive layers in the staircase structure, and a contact is formed within the spacer in each dummy source hole.

Abstract: A heterojunction bipolar transistor may include a base epitaxially grown on a collector, an emitter epitaxially grown on the base, the emitter and the base being patterned into a fin, and a silicon oxide layer formed on sidewalls of the fin, the silicon oxide layer separating the base from a spacer. The heterojunction bipolar transistor may include the spacer formed on top of the silicon oxide layer and an interlayer dielectric formed on top of the spacer. The heterojunction bipolar transistor may also include a silicon germanium oxide layer formed on sidewalls of the base. The base may be made of silicon germanium. The emitter and the collector may be made of silicon. The base may be doped with a p-type dopant. The emitter and the collector may be doped with a n-type dopant.

Abstract: A semiconductor layer (2,3) is provided on a substrate (1). A gate electrode (4), a source electrode (5) and a drain electrode (6) are provided on the semiconductor layer (3). A strongly correlated electron system material (12) is connected between the gate electrode (4) and the source electrode (5).

Abstract: A semiconductor device includes: first diode trench gates extending along a first main surface from a first end side of a cell region toward a second end side thereof opposite to the first end side, the first diode trench gates being disposed adjacent to each other at a first spacing; a boundary trench gate connected to end portions of the first diode trench gates and extending in a direction intersecting a direction of extension of the first diode trench gates; and second diode trench gates having end portions connected to the boundary trench gate and extending toward the second end side of the cell region.

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.