Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

Abstract: A photovoltaic device includes a substrate structure and a p-type semiconductor absorber layer. A photovoltaic device may include a CdSeTe layer. A process for manufacturing a photovoltaic device includes forming a CdSeTe layer over a substrate. The process includes forming a p-type cadmium selenide telluride absorber layer.

Abstract: According to some embodiments, AC chopping circuit includes a switching circuit, a synchronizing signal generating circuit, a switch driving circuit and an auxiliary power supplying circuit. In some examples, the switching circuit are coupled to an AC power source and a load. In certain examples, the synchronizing signal generating circuit provides a synchronizing signal which is related to a polarity of the AC power source. In some examples, the switching circuit is controlled based at least in part on the synchronizing signal.

Abstract: An electronic circuit board includes a printed circuit board and first and second electronic components. The printed circuit board includes a first insulating layer, a second insulating layer attached to the first insulating layer and in which is formed an open cavity, and a second conductive layer attached to the second insulating layer. The second conductive layer is treated to form a surface solder pad. The first electronic component is housed in the open cavity of the second insulating layer. The second electronic component is placed on the second insulating layer without overlapping with the open cavity. The first electronic component and the second electronic component each include a termination soldered on the surface solder pad, the surface solder pad being shared by the first and second electronic components.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: In certain aspects, a method for operating a memory device is disclosed. The memory device includes a plurality of memory planes. Whether an instruction is an asynchronous multi-plane independent (AMPI) read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and the AMPI read control signal is directed to a corresponding memory plane of the memory planes. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and the non-AMPI read control signal is directed to each memory plane of the memory planes.

Abstract: A method for starting a sensorless single-phase electric motor. The electric motor includes a permanent magnetic motor rotor, an electromagnetic motor stator having a stator coil, a power electronics which energizes the stator coil, a current sensor which measures a current flowing in the stator coil, and a control electronics which controls the power electronics. The control electronics is connected with the current sensor. The method includes energizing the stator coil with an alternating drive voltage, monitoring a drive current which is generated in the stator coil by the alternating drive voltage, and commutating the alternating drive voltage whenever the drive current reaches a predefined positive current threshold value or a predefined negative current threshold value.

Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.

Abstract: An electronics assembly includes a motor controller electronics arrangement with a solid-state switch array, a feeder cable connected to the motor controller and in electrical communication with the solid-state switch array, and a phase change material body. The phase change material body is thermally coupled to the feeder cable and arranged outside of the motor controller to limit conduction of heat generated by resistive heating of the feeder cable into the motor controller and through the feeder cable. Vehicles, electrical systems, and methods of cooling feeder cables in motor controller electronics arrangements are also described.

Abstract: The present invention relates to a close-contacting module capable of bringing a solar photovoltaic panel and a thermal collector of a solar photovoltaic-thermal panel into close contact without creating an interface. The close-contacting module comprises: a plurality of elastic members (36) which provide an elastic force that presses the thermal collector (20) toward the solar photovoltaic panel (10) from the backside of the thermal collector (20); a support member (35) for supporting the elastic members (36); and a pair of clips (31, 32, 33) provided at both ends of the support member (35) to fix the support member (35) to the edges of the solar photovoltaic-thermal panel (1).

Abstract: A bi-directional solid state switch includes: a first bus bar; a second bus bar; a first solid state switch implemented on a first printed circuit board (PCB), the first solid state switch including: a first control terminal; a first terminal electrically connected to the first bus bar; and a second terminal; and a second solid state switch implemented on a second PCB, the second solid state switch including: a second control terminal; a third terminal electrically connected to the second terminal of the first solid state switch; and a fourth terminal electrically connected to the second bus bar.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each target memory cell is programmed into one of K intermediate levels based on the corresponding piece of N-bits data, wherein 2N-1<K<2N. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the corresponding piece of N-bits data.

Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.

Abstract: An electronic circuit has three circuit carriers and two semiconductor components. A first semiconductor component contacts with its upper side an underside of a first circuit carrier, and with its underside an upper side of a second circuit carrier. The first circuit carrier has vias, with a first via connecting the first semiconductor component to a first conducting path and a second via connecting a connection element forming a second conducting path providing an integral connection between the circuit carriers. A second semiconductor component contacts the underside of the first circuit carrier and is electrically connected to the first or second conducting path. An underside of the second semiconductor component contacts an upper side of the third circuit carrier. A lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of both the second and the third circuit carrier.

Abstract: In certain aspects, a method for operating a memory device is disclosed. The memory device includes memory planes and multiplexers (MUXs). Each MUX includes an output coupled to a respective one of the memory planes, a first input receiving a non-asynchronous multi-plane independent (AMPI) read control signal, and a second input receiving an AMPI read control signal. Whether an instruction is an AMPI read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and a corresponding MUX is controlled to enable outputting the AMPI read control signal from the second input to the corresponding memory plane.

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Abstract: According to a certain embodiment, the semiconductor integrated circuit includes a multi-chip package comprising a plurality of memory chips, and a controller configured to control the multi-chip package. Each of the plurality of memory chips includes a logic control unit including a logic unit circuit configured to detect a potential from a wiring pad. The logic unit circuit determines a master chip or a slave chip on the basis of the potential detected from the wiring pad, the master chip transmits a pulse count and a status response command to the slave chip, so that the slave chip sets a logical unit number of its own memory chip, and the master chip sets a total number of chips loaded on the basis of status information from the slave chip.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: Embodiments provide a scheme for non-parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller is configured to: generate multiple optimal read threshold voltages corresponding to multiple sets of two cumulative distribution function (CDF) values, respectively; perform read operations on the cells using a plurality of read threshold voltages; generate cumulative mass function (CMF) samples based on the results of the read operations; receive first and second CDF values, selected from among a plurality of CDF values, each CDF value corresponding to each CMF sample; and estimate an optimal read threshold voltage corresponding to the first and second CDF values, among the multiple optimal read threshold voltages.

Abstract: Methods, systems, and devices that support techniques for programming self-selecting memory are described. Received data may include a first group of bits that each have a first logic value and a second group of bits that each have a second logic value. The first and second group of bits may be stored in a first set of memory cells and a second set of memory cells, respectively. A first programming operation for writing the second logic value to both the first and second set of memory cells and verifying whether the second logic value is written to each of the first set of memory cells, the second set of memory cells, or both may be performed. A second programming operation may write the first logic value to either the first set of memory cells or the second set of memory cells based on a result of the verification.