Patents Examined by T. Dinh
  • Motor controller
    Patent number: 11722083
    Abstract: A motor controller comprises a switch circuit, a pre-driver, a duty cycle control circuit, a current limit circuit, a pulse width modulation control unit, and a resistor. The motor controller is configured to drive a motor, where the motor has a motor coil and a maximum rated current. The switch circuit is configured to supply a motor current to the motor coil. The pre-driver generates a plurality of driving signals to control the switch circuit. The current limit circuit may store a current limit graph. The motor controller attains a function of maintaining a fixed output power by a plurality of current limit values, where each of the current limit values is less than or equal to the maximum rated current.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 8, 2023
    Assignee: Global Mixed-mode Technology Inc.
    Inventor: Chien-Lun Chu
  • Surface mount device bonded to an inner layer of a multi-layer substrate
    Patent number: 11723150
    Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Timing parameter adjustment mechanisms
    Patent number: 11721395
    Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Daniele Balluchi
  • Semiconductor device
    Patent number: 11721633
    Abstract: A circuit pattern, which is a second negative electrode wiring, and a horizontally extending area of a circuit pattern, which is a first negative electrode wiring, are connected electrically and mechanically by a vertically extending area of the circuit pattern and wires, which are an inter-negative-electrode wiring. As a result, N terminals and N1 terminals are equal in potential in a semiconductor device. The N terminals of a converter circuit section and the N1 terminals of an inverter circuit section are electrically connected to make the N terminals and the N1 terminals equal in potential.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 8, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaki Takahashi, Kousuke Komatsu, Rikihiro Maruyama
  • Techniques for determining memory cell read offsets
    Patent number: 11721398
    Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, Jingyuan Miao
  • Motor control apparatus and method of operating the same
    Patent number: 11716041
    Abstract: A motor control apparatus receives a DC power source through a DC terminal and is coupled to a motor. The motor control apparatus includes a brake, an inverter, and a controller. The brake is coupled to the inverter. The brake includes an energy-consuming component and a switch component. The controller controls the inverter to convert the DC power source to drive the motor. When the controller determines that the DC power source is interrupted, the controller stops controlling the inverter, and the switch component is self-driven turned on so that a back electromotive force generated by the motor is consumed through the energy-consuming component.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 1, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Te-Wei Wang, Yi-Kai Peng, Chen-Yeh Lee
  • Nonvolatile memory device including a fast read page and a storage device including the same
    Patent number: 11715516
    Abstract: A nonvolatile memory device including: a memory cell array, the memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells is a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cells with one read voltage and at least two normal read pages of the memory cells with the same number of read voltages.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 1, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunjung Lee, Chanha Kim, Kangho Roh, Heewon Lee
  • Flexure bearing assembly
    Patent number: 11716051
    Abstract: Solar trackers that may be advantageously employed on sloped and/or variable terrain to rotate solar panels to track motion of the sun across the sky include bearing assemblies and other mechanical features configured to address mechanical challenges posed by the sloped and/or variable terrain that might otherwise prevent or complicate use of solar trackers on such terrain.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: August 1, 2023
    Assignee: Nevados Engineering, Inc.
    Inventors: Yezin Taha, Amitoj Gill
  • Rotary electric machine control device
    Patent number: 11716048
    Abstract: A current detection unit includes current detection elements provided to phases on a high potential side of an upper arm element or on a low potential side of a lower arm element. A detection target element is the upper arm element or the lower arm element to which the current detection elements are provided. A target duty is a duty ratio of the detection target element. The control unit includes a current acquisition unit, an energization control unit, and an abnormality determination unit. The current acquisition unit acquires a current detection value from the current detection unit. The abnormality determination unit performs an abnormality determination based on the current detection value. The abnormality determination unit varies a determination threshold, which is used for the abnormality determination based on the current detection value, according to the target duty.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: August 1, 2023
    Assignee: DENSO CORPORATION
    Inventors: Kouichi Nakamura, Nobuyori Nakazima, Go Endoh
  • Compound and photoelectric device, image sensor and electronic device including the same
    Patent number: 11713326
    Abstract: A compound of Chemical Formula 1, and an organic photoelectric device, an image sensor, and an electronic device including the same are disclosed: In Chemical Formula 1, each substituent is the same as defined in the detailed description.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 1, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jisoo Shin, Chul Baik, Sung Young Yun, Taejin Choi, Kyung Bae Park, Gae Hwang Lee, Yeong Suk Choi, Chul Joon Heo, Hye Rim Hong
  • Data-based polarity write operations
    Patent number: 11710528
    Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Nevil N. Gajera, Hongmei Wang, Mingdong Cui
  • Apparatus for establishing a negative body potential in a memory cell
    Patent number: 11710525
    Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
  • Shield case and electronic circuit module
    Patent number: 11711889
    Abstract: A shield case, joined to a circuit board on which electronic components are mounted and covering the electronic components, has a top plate portion covering the electronic components, and a plurality of terminal leg portions formed in a way of projecting in a direction intersecting with the top plate portion from a peripheral edge portion of the top plate portion. Each of the plurality of terminal leg portions has: a leg portion stretching from the top plate portion; a terminal portion which extends in a direction intersecting with the leg portion from a front-end of the leg portion and is joined to the circuit board; and an expansion terminal portion which is formed by bending a front-end portion of each of the terminal portions along an end surface of the circuit board and has a length exceeding a thickness of the circuit board.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: July 25, 2023
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Mitsuhiro Nakamura
  • Apparatuses and methods for organizing data in a memory device
    Patent number: 11710524
    Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Aaron P. Boehm, Fa-Long Luo
  • Methods and systems for improving access to memory cells
    Patent number: 11705211
    Abstract: The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Riccardo Muzzetto, Umberto Di Vincenzo, Ferdinando Bedeschi
  • Dual address encoding for logical-to-physical mapping
    Patent number: 11704252
    Abstract: Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Jonathan S. Parry
  • Semiconductor memory system
    Patent number: 11705444
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: July 18, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Solar electrical generator
    Patent number: 11705858
    Abstract: A solar electrical generator comprising an outer wall (1, 2) arranged to partially surround a cavity. A hub (3) is provided within the cavity wherein the outer face (4) of the wall is provided with solar cells (5). At least one of the hub (3) and the inner face (6) of the wall are provided with solar cells (5).
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 18, 2023
    Assignee: SOLIVUS LIMITED
    Inventors: Jo Parker-Swift, James Baker, Ben Crundwell
  • Semiconductor device
    Patent number: 11705442
    Abstract: According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: July 18, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Atsushi Hosokawa, Yasuhisa Shintoku, Yasukazu Noine, Yoshiharu Katayama
  • Antistatic structure and air-conditioner
    Patent number: 11703252
    Abstract: An antistatic structure includes a casing, an element disposed in the casing, and a first conductive member disposed on an inner face of the casing and configured to send static electricity to a ground. The first conductive member is at least partially disposed around a region opposite the element in the casing.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 18, 2023
    Assignee: Daikin Industries, Ltd.
    Inventor: Takayuki Hattori