Patents Examined by T. R. Sundaram
  • Patent number: 6459290
    Abstract: There are provided plural integrated circuits a to i in which a self-diagnostic result obtained from a self-diagnostic circuit 12 is outputted and controlled by select signals 1, 2, 3 supplied from the outside, and each the self-diagnostic result of the plural integrated circuits is respectively supplied to one monitor through a determination signal line every plural self-diagnostic results and control is performed by control signals 1, 2, 3 so that any one of the self-diagnostic results of the plural integrated circuits supplied to the one monitor is outputted.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 1, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshikazu Nishikawa, Hideo Miyazawa, Hirozo Tanaka
  • Patent number: 6456098
    Abstract: In the method for testing a memory cell, a test voltage is applied to a memory cell and the test voltage is changed, preferably in incremental or decremental steps, during the testing. From the shape of the hysteresis of the memory cell it is determined whether or not the memory cell is a weak or substandard memory cell.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: September 24, 2002
    Assignee: Infineon Technologies AG
    Inventor: Peter Pöchmüller
  • Patent number: 6456054
    Abstract: For a throw-away tip provided with a sensor line of a conductive film, no technique has been established for connecting the sensor line to an external detection circuit and the like without any trouble. A throw-away tip 71 generally has an inward side face 88 and a rear side face 89 which are respectively restricted by an inward restriction face 95 and a rear restriction face 94 of a holder 92 for prevention of wobble and displacement of the throw-away tip 71 when the throw-away tip 71 is mounted in the holder 92. The inward side face 88 and the rear side face 89 are brought into abutment or intimate contact with the inward restriction face 95 and the rear restriction face 94, respectively. Therefore, the side faces (restricted faces) 88, 89 of the tip are not exposed but protected by the restriction faces 95, 94 of the holder with the tip being attached to the holder.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: September 24, 2002
    Assignee: Kyocera Corporation
    Inventor: Hideaki Kataoka
  • Patent number: 6452374
    Abstract: A radio-frequency reception arrangement for a magnetic resonance apparatus has a number of independent antennas and pre-amplifiers. The number of pre-amplifiers is less than the number of independent antennas. A switching matrix is arranged between the pre-amplifiers and the antennas for selective, signal-dependent connection of the pre-amplifiers to the antennas.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: September 17, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventor: Ludwig Kreischer
  • Patent number: 6448789
    Abstract: The present invention concerns a detector for detecting seat occupancy with at least two flat electrodes and a separating medium that separates the two electrodes from each other. The invention provides that the separating medium (3) has at least one spacing zone (4) and one deformation zone (5), which has a greater compressibility than the spacing zone (4).
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: September 10, 2002
    Assignee: W.E.T. Automotive System, AG Aktiengesellschaft
    Inventor: Juergen Kraetzl
  • Patent number: 6445190
    Abstract: A continuity checking device for a connector which comprises a connector holding part 3, a checking part 11 including continuity checking pins 5 capable of contacting with terminals 4, and insertion checking pins 8 which can be inserted into spaces where flexible locking lances 7 of the connector are deflected, the checking part being movable back and forth with respect to the connector holding part, and links 12 which are connected to the checking part at its one end and connected to an operating lever 13 at the other end, wherein the insertion checking pins 8 are immovably fixed inside the checking part, whereby a gap 14 is created between the checking part 11 and the connector holding part 3, when the insertion checking pins are abutted against the flexible locking lances 72. Each of the links 12 includes a displacement absorbing mechanisms.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: September 3, 2002
    Assignee: Yazaki Corporation
    Inventor: Takayuki Sato
  • Patent number: 6441634
    Abstract: A method of electrically testing pixel functionality is provided comprising releasably disposing a wafer in a socket. The wafer has at least one baseplate comprised of cathode emitters arranged in pixels. The socket has pads. The socket pads are contacted with test pins, and each of the pixels is addressed individually, thereby causing the cathode emitters to emit electrons in a current. The current is collected from each of the pixels on an anode screen. Alternatively, the anode card may have pins, and these pins contact pads on the baseplate. The baseplate, or substrate with baseplates, does not require a socket with pins.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: August 27, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Jim Browning, Charles M. Watkins, David A. Cathey
  • Patent number: 6441621
    Abstract: A waveform observing jig for observing a waveform of a signal outputted from a predetermined signal terminal, comprises: a contact for a signal, for contacting with a signal terminal of a board to be observed, and a plurality of contacts for a ground, for contacting with a ground pattern of the board to be observed, wherein at least one contact for a ground is in contact with the ground pattern of the board to be observed when the contact for a signal is in contact with a predetermined signal terminal of the board to be observed.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: August 27, 2002
    Assignee: Ando Electric Co., Ltd.
    Inventor: Takahiro Nagata
  • Patent number: 6433531
    Abstract: This invention discloses a method of instantaneous frequency measurement. The frequency band of interest is divided into a number of virtual sub-bands. Each sub-band is folded into a common baseband by a band folding down converter. Frequency measurement is achieved in a two part process, part 1 determines the center frequency of the virtual sub-band, while part 2 determines the baseband frequency, the frequency within the virtual sub-band. Both components of the RF frequency are then combined to form the frequency measurement. The frequency determinations for both sub-band frequency and baseband frequency are made by digital processing of the baseband phase measurements. The baseband phase is measured by a multi bit phase sampler, an integral part of the invention.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: August 13, 2002
    Inventor: Zvi Regev
  • Patent number: 6429662
    Abstract: An internal fault indicator for an electrical device is triggered by a sudden increase in pressure as occurs when an insulation failure creates an electric arc. The heat released in the arc is transferred onto the surrounding volume causing localized overheating, vaporization and decomposition of the insulating material. The resulting pressure surge moves a diaphragm. The movement of the diaphragm releases a spring driven plunger from a barrel which extends through the housing of the electrical device. Prior to activation the plunger is held in an “armed” position by a retaining pin. Upon triggering, the plunger is pushed by the spring until it protrudes from the housing to provide a visual signal of the internal fault. A pressure relief valve may be integrated with the internal fault indicator.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: August 6, 2002
    Assignee: IFD Corporation
    Inventors: Nikola Cuk, Stuart H. Hicks, Robert Suggitt
  • Patent number: 6429664
    Abstract: A method and device for determining the concentration of a medium other than air in an air/medium aerosol. The dielectric constant of the medium is measured using microwaves in a hollow conductor, with the aerosol passing through a neutral tube intersecting the hollow conductor. The microwave signal which propagates in the hollow conductor is subjected to attenuation and a phase shift due to the difference between the dielectric constant of the medium and that of air, the phase shift of the microwave signal being measured by taking into account the active path length (the tube in the cross section of the hollow conductor).
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: August 6, 2002
    Assignee: SIG Combibloc GmbH
    Inventor: Hartmut Kanngiesser
  • Patent number: 6429667
    Abstract: A monitor for electrically testing energy beam dose or focus of a layer formed on a substrate by lithographic processing. The monitor comprises a substrate having in a lithographically formed layer an array of electrically conductive elements comprising a plurality of spaced, substantially parallel elements having a length and a width, with the individual elements being electrically connected, and the lengths of the elements being sensitive to dose and focus of an energy beam in lithographically forming the layer. The monitor further includes at least one pad electrically connected to the array to apply current through the array elements. Upon applying a voltage across the array elements, the suitability of dose or focus of the lithographically formed layer may be determined by the resistance of the array. Preferably, ends of the individual elements are aligned along essentially straight lines to form an array edge.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventors: Christopher P. Ausschnitt, Christopher E. Obszarny
  • Patent number: 6429665
    Abstract: An impedance detection circuit includes a circuit input having a first contact and a second contact, a reference voltage rail coupled to the first contact, and a memory cell having a data node coupled to the second contact and an output. When the memory cell is read, the logic state of the output provides an indication of an impedance coupling the first and second contacts at the circuit input. The impedance detection circuit can be utilized to sense resistive and capacitive inputs and has any number of applications, including use as a digital hygrometer and as a fingerprint sensor.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shyamalindu Ghoshal
  • Patent number: 6429645
    Abstract: A verification gauge for verifying the operation of an inspection system for inspecting the leads of an electronic package, particularly a ball grid array. The gauge has a predetermined mechanical relationship to a mechanical parameter of the leads of the electronic package so that when the inspection system is used to inspect the gauge, a reading will indicate whether the inspection system is properly set up for the mechanical parameter. The gauge may be configured to substantially emulate the structural configuration, including the particular size, shape and lead pattern, of the electronic package. The gauge may be used to verify the calibration or the predefined limit of the inspection system for the mechanical parameter, including lead coplanarity, lead pitch, missing lead and lead deformation parameters.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: August 6, 2002
    Assignee: EMC Corporation
    Inventor: Stuart D. Downes
  • Patent number: 6426636
    Abstract: A nonresilient rigid test probe arrangement which is designed for testing the integrity of silicon semiconductor device wafers or chips, and which eliminates pliant conditions encountered by current text fixtures, which are adverse to the attainment of satisfactory test results with rigid probes. The test system interface assembly includes a rigid ceramic substrate which forms a pedestal over which the rigid probe makes electrical contact. A PC board is located on the opposite side of the ceramic substrate. A clamp ring retains the PC board to a test head system with mating precision reference surfaces formed therebetween. Pogo pin connectors extend between the PC board and the test head system. A stiffening element having a control aperture is bolted through the PC board to the clamp ring, all of which form a rigid test probe arrangement.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Gobinda Das, Steven J. Duda, Paul M. Gaschke, Angelo M. Giaimo, Frederick L. Taber, Jr., John F. Vetrero
  • Patent number: 6426633
    Abstract: A method for monitoring a rotational angle sensor on an electrical machine. It is desired to provide a method that enables fault detection at both high speeds and low speeds of the rotor. The electrical power of the machine is measured and a power value is estimated using the output signal of the rotational angle sensor, a residual being formed from the measured power and the estimated power and the time curve of the residual being monitored.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: July 30, 2002
    Assignee: Danfoss Drives A/S
    Inventor: Claus Thybo
  • Patent number: 6426630
    Abstract: An electrostatic voltmeter (ESV) and a method thereof provides an electrical signal proportional to an electrostatic potential. The ESV includes a high voltage input section that receives a high voltage signal representative of an electrostatic potential. The high voltage signal input section then generates a current signal representative of the electrostatic potential. The current signal is applied to a control and sensing circuit. A high voltage current source is connected between the high voltage input section and a high voltage potential. The high voltage current source acts as an active load for the control and sensing circuit. A voltage level determining section is connected to a node between the high voltage input section and the high voltage current source for providing an electrical signal proportional to the electrostatic potential. The EVS disclosed herein is particularly useful in measuring electrostatic potential of a photoreceptor to control imaging in an electrophotographic imaging system.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: July 30, 2002
    Assignee: Xerox Corporation
    Inventor: Alan J. Werner, Jr.
  • Patent number: 6424157
    Abstract: A system and method for monitoring and reporting on the condition of a vehicle battery which measures battery voltage and current drain during engine start, and computes the battery dynamic internal resistance (IR) and dynamic polarization resistance (PR) from these quantities. Also, the quiescent voltage (QV) of the battery, which is that measured while the vehicle electrical system has a current drain of from 0 to a predetermined amount, is measured and the battery state-of-charge (SoC) is computed from the QV. From these quantities, calculations are made of quantities such as rate of change of dynamic IR and PR to analyze battery condition, rate of change of QV and SoC to predict the time during which the battery can still start the engine, and minimum ambient temperature at which the battery will be able to start the engine, and of other conditions.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: July 23, 2002
    Assignee: AlliedSignal, Inc.
    Inventors: Bernard P. Gollomp, Thirumalai G. Palanisamy, Douglas Vernick
  • Patent number: 6420894
    Abstract: A method and a circuit for testing an integrated circuit are disclosed. In one embodiment, a self-resetting dynamic circuit, also known as a fireball circuit, contains a scan circuit and at least one Set Dominant Latches (“SDL”) where each SDL includes a keeper node. When scan clock is active, the scan data propagates from the scan circuit to the self-resetting dynamic circuit through the keeper node.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: July 16, 2002
    Assignee: Intel Corporation
    Inventors: Xia Dai, Terry Chappell
  • Patent number: 6420880
    Abstract: A semiconductor testing process effectively determines the integrity of a large capacitive structure buried within an integrated circuit. According to one example embodiment, a process of testing the oxide integrity of a circuit involves selecting a large gate oxide structure or structures that can be isolated from leakage paths. The dielectric integrity of the structure is tested by stressing the structure via voltage settings, comparable to a supply voltage, across its two terminals. The structure is connected to a current-sensitive node in-the integrated circuit across the two terminals. Other circuits connected to the current-sensitive node are shut off so that the current-sensitive node should be an island relative to other current paths. The leakage current at the current-sensitive node is then measured and compared with a reference level. From the measurements and comparison, a quality factor indicative of the dielectric integrity in the structure is determined.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: July 16, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Edward E. Miller