Abstract: The semiconductor component has an electronic circuit in or on a main surface of a semiconductor chip. Connecting surfaces or pads are disposed on the main surface of the semiconductor chip and are electrically coupled to the electronic circuit. This allows electrical access to the circuit from outside the chip. The electronic circuit is operable in a test mode, which can normally be carried out in the wafer composite of the semiconductor chips and in which an externally supplied test signal is applied to a predetermined pad, and in an operating mode in which operating signals are applied to the pads. At least one pad is assigned a switching device which allows changing the function of that pad from the test mode to the operating mode.

Abstract: An on-line somatic cell analyser and a method for evaluating the quantity of somatic cells present in a sample of milk are provided. A flow cell is connected to a milking hose and admits a constant volume of sampled milk into a flow chamber. A probe with two electrodes is positioned in a zone of optimal sensing inside the flow chamber and provides a modulated signal with an intensity value corresponding to the number of sodium ions present in the sample. A detection unit receives the modulated signal and generates a ion count signal whenever the number of sodium ions is above a reference value. A control unit converts the ion count signal into a somatic cell count (SCC) score. A step graph comprising a plurality of SCC thresholds defining a plurality of milk categories is stored in a memory and used by the control unit to classify the sample in a quality category according to the SCC score of the sample.

Abstract: A host register interface testing system and method are disclosed. The system includes a host register unit including information that is indicative of a set of host registers corresponding to a programmable device under test. The system further includes a rule set unit including information that is indicative of constraints on values that the set of host registers may assume and a test setup generator configured to access the host register unit and the rule set unit and to generate a set of test setups based on the contents of the host register unit and the rule set unit where each test setup corresponds to a valid state of the set of host registers. In one embodiment, the test setup generator is suitable for applying a test setup from the set of test setups to the device under test. In one embodiment, the system may further include a verifier configured to receive the output of the device under test and, based thereon, for determining the functionality of the device under test.

Abstract: A burn-in system uses a board for testing modules disposed like a matrix in the board. A circuit configuration includes module terminals for the modules in the board. Input/output channels are each connected to a respective one of the module terminals. Diodes are each connected to a respective one of the input/output channels. A scan signal terminal is connected to the diodes for activating the module terminals in groups with scan signals.

Abstract: A device is disclosed for inspecting an object of electrically conductive material, in which a non-static-signal transmitter generates an electromagnetic field in the object, and a receiver measures the variations of the eddy current generated by the non-static electromagnetic field and produces a signal representing the decay of the eddy current. The non-static-signal transmitter is provided with at least two laterally spaced-apart emitters for emitting an electromagnetic field, which emitters are, during normal operation, so driven that the resulting electromagnetic field in the central region between the emitters is intensified.

Abstract: A pair of copper coils are embedded in the foil strip. A first coil of the pair generates an electromagnetic field that induces eddy currents on the surface, and the second coil carries a current influenced by the eddy currents on the surface. The currents in the second coil are analyzed to obtain information on the surface eddy currents. An eddy current probe has a metal housing having a tip that is covered by a flexible conductive foil strip. The foil strip is mounted on a deformable nose at the probe tip so that the strip and coils will conform to the surface to which they are applied.

Abstract: For the electrical testing of base material for manufacturing printed circuit boards, firstly smooth edges to the copper layers of the base material, free of deformation, are produced, preferably in a milling process, which base material is subsequently subjected to testing for a sufficiently high level of electrical resistance between the two copper layers. Successful resistance testing is followed by testing for the dielectric strength of the insulating layer of the base material by measuring the current conduction produced as a result of a disruptive breakdown. This process serves to reduce the amount of processed base material which is rejected, on which, at the present state of the art, there is no electrical testing prior to processing.

Abstract: Microwaves are respectively propagated through a reference fluid and fluid to be measured, both contained in a detection pipe body, and as a result, a first phase lag &thgr;1 and a second phase lag &thgr;2 can be determined on the basis of the microwaves by a phase lag measuring circuit. Then, a density computing circuit subtracts the first phase lag &thgr;1 from the second phase lag &thgr;2 to determine a phase difference &Dgr;&thgr;. When computing the density of matter in the fluid on the basis of the phase difference &Dgr;&thgr;, the density computing circuit performs density computing processing such that a real second phase lag &thgr;2 satisfies the following equation &thgr;2=&thgr;2′+N×360° where N is the number of rotations, and &thgr;2′ is an apparent phase lag obtained by the phase lag measuring circuit.

Abstract: A method, apparatus and computer program product for identifying electrostatic discharge (ESD) damage to a thin film device. The method includes (1) determining a cold resistance of the thin film device, (2) determining a hot resistance of the thin film device, (3) calculating a heating delta resistance (HDR) from the hot and cold resistances and (4) comparing the HDR to a threshold value to ascertain if the thin film device has suffered ESD damage. The HDR of the thin film device is characterized by the following relationship: HDR=(hot resistance-cold resistance)/(cold resistance).

Abstract: A test socket for testing a vertical surface mount packaged semiconductor device, the test socket including a test substrate, a support member, and clamps. The test substrate includes terminals which are electrically connectable to a testing device. The shape of the support member is complementary to the shape of the bottom surface of leads extending from the vertical surface mount packaged semiconductor device. The shape of the clamps is complementary to the top surface of the leads. The test substrate may also define lead alignment notches around one or more of the terminals. Upon placement of a vertical surface mount packaged semiconductor device on the test substrate, the leads are aligned with their corresponding terminals, then placed against the terminals and the support member. The clamps are then placed against the leads, biasing each of the leads against the support member and its corresponding terminal.

Abstract: A load sensing circuit detects an input load signal across a transformer based on changes in electric current conducted through a primary winding of the transformer. A triangle wave signal is provided to the primary winding of the transformer to induce a corresponding signal at a secondary winding of the transformer. The signal at the secondary winding varies as a function of the input load signal to effect corresponding changes in the electric current conducted through the primary winding. An output circuit provides an indication of the value of the load signal based on the current conducted through the primary winding.

Abstract: A system for, and method of, testing a sample integrated circuit (IC) and a test apparatus incorporating the system or the method. The sample IC includes symmetrical circuits having corresponding intrinsic leakages that depend upon a process employed to manufacture the sample IC. In one embodiment, the system includes: (1) data storage circuitry that contains data derived statistically from exemplary ICs manufactured according to the process and determined to be acceptable and (2) test circuitry, associated with the data storage circuitry, that measures the corresponding intrinsic leakages to determine whether the sample IC is acceptable.

Abstract: The device may be used to, for example, function test sensors in high voltage plants and signal boxes. The device makes it possible to function test sensors in high voltage plants, independent of where the sensors are located. The elongated device has one end that is provided with an insulated handle part and a flexible component that has a light generating part at an outer end thereof. The light generating part emits a light that is similar to the light of an electric arc.

Abstract: An integrated circuit device is disclosed having a BIST Uinit with recolfiLgurable data retention testing for a memory array. In one embodiment, the integrated circuit device includes a memory array, a BIST unit, an externally-programmable pause count register, and a pause counter. The BIST unit is configured to apply a test pattern of memory accesses to the memory array. The test pattern preferably includes a first phase for writing data values to the memory array, a second phase for stressing the memory array, and a third phase for verifying the data values after the array has been stressed. The length of the second phase is determined by the count stored in the externally-programmable register. The count may be loaded into the pause counter by the BIST prior to the second phase. In the second phase, the BIST unit asserts a pause signal which causes the pause counter to suppress the clock signal to the BIST unit during the second phase, thereby suspending the BIST unit's activity.

Abstract: A raster scan digital signal acquisition and waveform display instrument displays a dot representing a signal event with a color parameter in accordance with the value of a corresponding data word stored in a raster scan memory. A user interface control element supplies a single color parameter control value from which multiple independent control values for influencing the values of the data words stored in the raster scan memory in response to the single color parameter control value are generated.

Abstract: A hot carrier measuring circuit of the present invention, which measures the characteristic degradation of a semiconductor device due to AC operation, includes a pulse generator generating at least two pulse signals which are partially overlapped with each other and have various duty ratios, a level shifter shifting the pulse signal which are generated in the pulse generator to a desired voltage level, and a measuring device receiving the pulse signals outputted from the level shifter to at least one terminal thereof.

Abstract: A waveform translator in which the frequency spectrum of a repetitive non band limited input signal is translated to an equivalent frequency spectrum which is harmonically related to a fixed reference frequency. In the waveform translator a synthesized source generator and a synthesized receive generator are made coherent. The source generator drives a DUT, and the receive generator coupled to a sampler, samples the DUT to produce a non band limited difference signal harmonically related to the fixed reference frequency. The difference signal is digitized in an analog to digital converter which is clocked at the reference frequency and produces a predetermined integer number of data points per cycle corresponding to the input signal. A computer is coupled to the waveform translator for DC to 75 GHz oscillography.

Abstract: The present invention finds the overall concentration of a mixture in the following way. It measures the measurement sensitivity of substance C, of which the constituent composition varies, out of multiple substances A, B and C using sensitivity measuring microwave type concentration meter 17. It then inputs this measurement result to calibration curve gradient setter 20. It then finds the calibration curve gradient using a computing device which possesses the relationship of the measurement sensitivity of the single substance of which the constituent composition varies to the calibration curve gradient that finds the overall concentration of substances A, B and C. It then sets this calibration curve gradient in mixture concentration measuring microwave type concentration meter 18.

Abstract: A method for space-charge measurement in a coaxial cable comprising an inner conductor (2), a cable screen (3) and an electric insulation (4) between the inner conductor and the cable screen, wherein the cable screen is removed on both sides of a measurement region, an electric voltage pulse is generated by an electric pulse generator (10) and is applied over part of the insulation (4) of the cable within the measurement range, an acoustic signal, in the presence of space charges in the cable insulation, is generated by the voltage pulse in cooperation with the space charges and a possible acoustic signal is recorded by a sound-recording device (8). A grounded annular outer electrode (7) is applied around the measurement region, the sound-recording device is arranged in direct contact with the annular outer electrode, the voltage pulse is applied to the cable screen on both sides of the measurement region and is connected, via the impedance of the cable, to the inner conductor of the cable.

Abstract: A test station for use with automated test equipment (ATE) in testing printed circuit boards (PCBs). The test station comprises a support frame to which are attached substantially identical test wells for sequentially performing tests on the PCBs. The test wells are attached to the frame through a mechanism that allows the test wells to be adjustably positioned between an idle position and a testing position that is in proximity with the ATE. Each of the test wells contains upper and lower conveyor segments and a test head disposed between the conveyor segments. The conveyor segments of the respective test wells variously align in accordance with vertical movement of the test wells so as to enable transverse movement of the PCBs into, through and out of the test station.