Patents Examined by Telly Green
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Patent number: 9871165Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.Type: GrantFiled: May 22, 2017Date of Patent: January 16, 2018Assignee: The Silanna Group Pty LtdInventors: Petar Atanackovic, Matthew Godfrey
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Patent number: 9871148Abstract: A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus.Type: GrantFiled: October 28, 2016Date of Patent: January 16, 2018Assignee: Sony CorporationInventors: Kyohei Mizuta, Tomokazu Ohchi, Yohei Chiba
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Patent number: 9871145Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.Type: GrantFiled: June 21, 2017Date of Patent: January 16, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
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Patent number: 9859818Abstract: A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.Type: GrantFiled: December 8, 2014Date of Patent: January 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Patent number: 9852870Abstract: The present invention is directed to a method for the fabrication of electron field emitter devices, including carbon nanotube (CNT) field emission devices. The method of the present invention involves depositing one or more electrically conductive thin-film layers onto a electrically conductive substrate and performing lithography and etching on these thin film layers to pattern them into the desired shapes. The top-most layer may be of a material type that acts as a catalyst for the growth of single- or multiple-walled carbon nanotubes (CNTs). Subsequently, the substrate is etched to form a high-aspect ratio post or pillar structure onto which the previously patterned thin film layers are positioned. Carbon nanotubes may be grown on the catalyst material layer. The present invention also described methods by which the individual field emission devices may be singulated into individual die from a substrate.Type: GrantFiled: May 23, 2011Date of Patent: December 26, 2017Assignee: CORPORATION FOR NATIONAL RESEARCH INITIATIVESInventors: Mehmet Ozgur, Paul Sunal, Lance Oh, Michael Huff, Michael Pedersen
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Patent number: 9853166Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.Type: GrantFiled: July 25, 2014Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 9853137Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.Type: GrantFiled: November 9, 2015Date of Patent: December 26, 2017Assignee: Infineon Technologies AGInventors: Moriz Jelinek, Johannes Georg Laven, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
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Patent number: 9852981Abstract: An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region. In accordance with the present application, the middle region of the anti-fuse includes at least a portion of the second metal structure that is located in a gap positioned between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material. A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure.Type: GrantFiled: April 13, 2016Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
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Patent number: 9852921Abstract: A substrate treating apparatus and a method of treating a substrate, the apparatus including a substrate treater that treats a substrate using a chemical solution, the chemical solution including a phosphoric acid aqueous solution and a silicon compound; and a chemical solution supplier that supplies the chemical solution to the substrate treating unit, wherein the chemical solution supplier includes a concentration measurer that measures concentrations of the chemical solutions, the concentration measurer including a first concentration measurer that measures a water concentration of the chemical solution; and a second concentration measurer that measures a silicon concentration of the chemical solution.Type: GrantFiled: June 7, 2016Date of Patent: December 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Hwan Kim, Ingi Kim, Mihyun Park, Young-Hoo Kim, Ui-soon Park, Jung-Min Oh, Kuntack Lee, Hyosan Lee
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Patent number: 9842836Abstract: A diode according to the present invention includes a semiconductor layer of a first conductivity type having an impurity concentration of 1×1016 cm?3 to 2.4×1017 cm?3, a Zener diode region of a second conductivity type formed selectively in the semiconductor layer and forming a pn junction with the semiconductor layer, a Schottky metal disposed on the semiconductor layer, forming a Schottky junction with the semiconductor layer, and having a work function of 3 eV to 6 eV, and a JBS (junction barrier Schottky) structure including a plurality of second conductivity type regions formed selectively in the Schottky junction region of the semiconductor layer.Type: GrantFiled: April 13, 2016Date of Patent: December 12, 2017Assignee: ROHM CO., LTD.Inventors: Kohei Makita, Teruhiro Koshiba
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Patent number: 9837395Abstract: A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.Type: GrantFiled: April 12, 2016Date of Patent: December 5, 2017Assignee: Renesas Electrics CorporationInventors: Hisashi Toyoda, Koichi Yamazaki, Koichi Arai, Tatsuhiro Seki
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Patent number: 9837639Abstract: According to one or more embodiments of the present invention, a display apparatus includes: a substrate; a display unit which is formed on the substrate and includes an emission area and a non-emission area; a first coating layer which is formed on the display unit and has an uneven area formed on the emission area; a first blocking layer which is formed on the non-emission area of the first coating layer; and a second blocking layer which is formed on the first blocking layer and prevents reflection of external light.Type: GrantFiled: March 9, 2017Date of Patent: December 5, 2017Assignee: Samsung Display Co., Ltd.Inventors: Hyun-Ho Kim, Soo-Youn Kim, Seung-Yong Song, Sang-Hwan Cho, Jin-Koo Kang, Seung-Hun Kim, Cheol Jang, Chung-Sock Choi, Sang-Hyun Park
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Patent number: 9837381Abstract: A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.Type: GrantFiled: September 30, 2015Date of Patent: December 5, 2017Assignee: INFINEON TECHNOLOGIES AGInventor: Alexander Heinrich
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Patent number: 9831166Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.Type: GrantFiled: January 4, 2017Date of Patent: November 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
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Patent number: 9831398Abstract: A method for producing a ceramic conversion element and a light-emitting device are disclosed. In an embodiment the method includes providing at least four functional layers, each being a green body or a ceramic, wherein first functional layer is formed as a first luminous layer comprising an oxide and configured to at least partially convert light of a first wavelength range into light of a second wavelength range, wherein a second functional layer is formed as a second luminous layer comprising a nitride and configured to at least partially convert light of the first wavelength range into light of a third wavelength range, wherein a third functional layer is formed as a first intermediate layer, wherein the first intermediate layer comprises an oxide, wherein a fourth functional layer is formed as a second intermediate layer, and wherein the second intermediate layer comprises a nitride or an oxynitride.Type: GrantFiled: January 20, 2015Date of Patent: November 28, 2017Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventor: Britta Göötz
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Patent number: 9831175Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.Type: GrantFiled: April 17, 2017Date of Patent: November 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Suraj Kumar Patil, Min-Hwa Chi
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Patent number: 9818708Abstract: A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.Type: GrantFiled: March 28, 2017Date of Patent: November 14, 2017Assignee: AMKOR TECHNOLOGY, INC.Inventors: Dong Hoon Lee, Do Hyung Kim, Seung Chul Han
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Patent number: 9818712Abstract: A device package includes a substrate having an active surface. Electrical connection bumps are deposited on the active surface and are arranged in an array having a perimeter. At least one electronic component is formed at a region of the active surface, where the region is located outside of the perimeter of the array of electrical connection bumps. When the device package is coupled with external circuitry via the electrical connection bumps, the region at which the electronic component is formed is suspended over the electronic circuitry. This region is subject to a lower stress profile than a region of the active surface circumscribed by the perimeter. Thus, stress sensitive electronic components can be located in this lower stress region of the active surface.Type: GrantFiled: January 14, 2015Date of Patent: November 14, 2017Assignee: NXP USA, Inc.Inventors: Paige M. Holm, Vijay Sarihan
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Patent number: 9806055Abstract: A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.Type: GrantFiled: April 28, 2016Date of Patent: October 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
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Patent number: 9806087Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.Type: GrantFiled: May 22, 2017Date of Patent: October 31, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Chandrasekar Venkataramani, Qiuji Zhao, Koe Sun Pak, Bai Yen Nguyen, Yoke Weng Tam