Abstract: A semiconductor device manufacturing method includes loading a substrate, on which a high-k film is formed, into a processing chamber, performing a reforming process by heating the high-k film through irradiation of a microwave on the substrate, and unloading the substrate from the processing chamber.

Abstract: A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area.

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract: Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

Abstract: A semiconductor memory element has MOS transistor for writing by a drain-avalanche hot electron. The MOS transistor has a semiconductor substrate, a first semiconductor layer formed on the semiconductor substrate, a floating gate provided on the first semiconductor layer through intermediation of a first insulating film, a channel region formed in a surface of the first semiconductor layer under the floating gate, and source region and a drain region provided on the first semiconductor layer so as to be in contact with the channel region. The channel region has a distribution of at least two kinds of carrier densities provided in at least two portions thereof disposed in parallel along a direction connecting the source region and the drain region.

Abstract: Semiconductor device packages comprise a first semiconductor device comprising a heat-generating region located on at least one end thereof. A second semiconductor device is attached to the first semiconductor device. At least a portion of the heat-generating region extends laterally beyond at least one corresponding end of the second semiconductor device. A thermally insulating material at least partially covers the end of the second semiconductor device. Methods of forming a semiconductor device packages comprise attaching a second semiconductor device to a first semiconductor device. The first semiconductor device comprises a heat-generating region at an end thereof. At least a portion of the heat-generating region extends laterally beyond an end of the second semiconductor device. The end of the second semiconductor device is at least partially covered with a thermally insulating material.

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Abstract: A resistor-equipped transistor includes a package that provides an external collector connection node (114, 134), an external emitter connection node (120, 140) and an external base connection node (106, 126). The package contains a substrate upon which a transistor (102, 122), first and second resistors, and first and second diodes are formed. The transistor has an internal collector (118, 138), an internal emitter (120, 140) and an internal base (116, 136) with the first resistor (104, 124) being electrically connected between the internal base and the external base connection node and the second resistor (108, 128) being electrically connected between the internal base and the internal emitter.

Abstract: A photoelectric conversion device includes an organic photoelectric conversion layer, and suppresses sensitivity degradation caused by the light irradiation. A photoelectric conversion device 100 is formed by stacking a first electrode layer 104, a photoelectric conversion layer 15 including an organic material, and a second electrode layer 108 on a substrate 101, in which the photoelectric conversion layer 15 has a bulk hetero structure of a P-type organic semiconductor and an N-type organic semiconductor, and a difference between an ionization potential of the P-type organic semiconductor and an apparent ionization potential of the bulk hetero structure is 0.50 eV or less. Accordingly, it is possible to suppress sensitivity degradation caused by the light irradiation.

Abstract: A semiconductor device has a field insulating film provided on a semiconductor substrate, and a fuse provided on the field insulating film and having a fuse trimming laser irradiation portion and fuse terminals. The semiconductor device further includes an intermediate insulating film covering the fuse, a first TEOS layer on the intermediate insulating film, an SOG layer for planarizing the first TEOS layer, a second TEOS layer on the SOG layer and on the first TEOS layer, a protective film on the second TEOS layer, and an opening portion above the fuse trimming laser irradiation portion in a region from the protective film to the first TEOS layer. A seal ring is provided on the intermediate insulating film so as to surround the opening portion. The seal ring is disposed over the fuse so as to overlap each of the fuse terminals in plan view.

Abstract: Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.

Abstract: Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer on an upper surface of the second electrode. The second electrode may be comprised of a second conductor, and the cap layer may have a composition that is free of titanium. The second electrode may be formed by etching a layer of a material formed on a layer of the second conductor to define a hardmask and then modifying the remaining portion of that material in the hardmask to have a comparatively less etch rate, when exposed to a chlorine-based reactive ion etch chemistry, than when initially formed.

Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.

Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.

Abstract: A semiconductor device includes a semiconductor substrate having a groove and an active region adjacent to the groove; a buried gate electrode in the groove; and a capacitor contact including a first portion and a second portion over the first portion. The first portion is greater in horizontal dimension than the second portion. The first portion has a bottom surface that is in contact with an upper surface of the active region.

Abstract: There is provided a semiconductor light emitting device and method of making the same, having a first conductivity type semiconductor layer; an active layer formed on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer formed on the active layer and including a plurality of holes; and a transparent electrode formed on the second conductivity type semiconductor layer.

Abstract: A light-emitting diode has a metal structure, a light-emitting chip, and a bowl structure. The metal structure has a platform and a heat sink. The platform has a top face, a first side, and a second side opposite to the first side. A first reflector and a second reflector respectively extend from the first side and the second side. The heat sink extends below the top face and has a drop from the bottom surfaces of the first reflector and the second reflector. The light-emitting chip is disposed on the top face. The bowl structure covers the outer surface of the metal structure and shields the bottom surfaces of the first reflector and the second reflector. A thermal dispassion surface of the heat sink is exposed from the bowl structure. An inner surface of bowl wall has a plurality of reflection structures to promote the light extraction efficiency.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

Abstract: A flat panel display having a thin-film transistor (TFT) and a pixel unit and a method of manufacturing the same are disclosed. In one embodiment, the method includes forming a step difference layer having a relatively high step and a relatively low step on a substrate and forming an amorphous silicon layer on the step difference layer along a height shape of the step difference layer. The method further includes crystallizing the amorphous silicon layer into a crystalline silicon layer and polishing the crystalline silicon layer to form a planarized surface of the crystalline silicon layer having no height differences so that the crystalline silicon layer remains on a region corresponding to the low step and an active layer is formed. According to this method, crystallization protrusions are effectively removed from the active layer, and thus, stable brightness characteristics of the display apparatus are guaranteed.